scholarly journals Bus Implementation Using New Low Power PFSCL Tristate Buffers

2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Neeta Pandey ◽  
Bharat Choudhary ◽  
Kirti Gupta ◽  
Ankit Mittal
Keyword(s):  
Power Consumption ◽  
Current Source ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Performance Parameters ◽  
Interesting Consequence ◽  
Spice Simulation ◽  
High Impedance ◽  
Parameter Variations ◽  
Feedback Source

This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.

New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies

2017 ◽  
Vol 26 (12) ◽  
pp. 1750186 ◽  
Author(s):  
Neeta Pandey ◽  
Bharat Choudhary ◽  
Kirti Gupta ◽  
Ankit Mittal
Keyword(s):  
Power Supply ◽  
Positive Feedback ◽  
Current Source ◽  
Propagation Delay ◽  
State Behavior ◽  
Maximum Reduction ◽  
And Performance ◽  
Feedback Source

This paper describes new sleep-based positive feedback source-coupled logic (PFSCL) tri-state inverter/buffer topologies. The tri-state behavior is obtained by disconnecting the circuit from both power supply and ground. This is achieved by placing additional transistors, driving the load transistor to cut off or disabling the current source. The combination of the three methods results in six new topologies. The functionality and performance of the proposed topologies is studied through SPICE simulations. A comparison with available sleep-based PFSCL tri-state buffer circuit shows a maximum reduction of 11% and 60% in the propagation delay and output enable time, respectively. The usefulness of the proposed topologies is illustrated through bus and D latch implementation.

scholarly journals Optimizing the Performance of MOS Stacks

2020 ◽  
Vol 16 (1) ◽  
pp. 85-98
Author(s):  
Sherif Sharroush
Keyword(s):  
Time Delay ◽  
Power Consumption ◽  
Figure Of Merit ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Scaling Factor ◽  
Worst Case ◽  
In Series ◽  
High Transition ◽  
Exclusive Or

CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.

scholarly journals Low-Power High-Speed Double Gate 1-bit Full Adder Cell

2016 ◽  
Vol 62 (4) ◽  
pp. 329-334 ◽  
Author(s):  
Raushan Kumar ◽  
Sahadev Roy ◽  
C.T. Bhunia
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Pass Transistor ◽  
Voltage Swing

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique

2016 ◽  
Vol 25 (12) ◽  
pp. 1650153
Author(s):  
Vinay Kumar ◽  
Anup Dandapat
Keyword(s):  
Power Consumption ◽  
Design Methodology ◽  
Propagation Delay ◽  
Combinational Circuits ◽  
Performance Parameters ◽  
Combinational Circuit ◽  
Feed Forward ◽  
Multiple Outputs ◽  
Simulation Results ◽  
Layout Area

Conventional combinational circuits are generally acyclic (feed-forward) but these circuits can have feedbacks (cycles) which will give more minimized expressions as compared to conventional combinational circuits. Deliberate incorporation of such cycles or feedbacks in conventional combinational circuits eventually results in reduction in number of literals in the expression of the combinational circuits. The reduction in literal counts decreases the number of gates required to implement the expressions of the combinational circuits. Hence, the decrease in number of gates leads to reduction in transistor counts or layout area for the circuits. A cyclic combinational circuit (CCC) is defined as the circuit whose output depends on present inputs only, but at the same time contains one or more feedbacks (cycles). This paper presents a simplified methodology for introduction of cycles (feedbacks) and finding expressions for the CCC. The methodology is applied on LGSynth93 benchmark circuits and a reduction up to 28% in literal counts for expressions of CCC was found which is higher than the reduction achieved by other methodologies. Further the methodology is applied to implement binary comparator which has got three multiple outputs using cyclic combinational technique. The circuits are verified through simulation in cadence virtuoso tools using 45[Formula: see text]nm technology. Based on simulation results, performance parameters like power consumption, propagation delay and layout area of CCC are compared with the conventional circuits.

DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS

2014 ◽  
Vol 23 (07) ◽  
pp. 1450092 ◽  
Author(s):  
PRABIR SAHA ◽  
DEEPAK KUMAR ◽  
PARTHA BHATTACHARYYA ◽  
ANUP DANDAPAT
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Boolean Logic ◽  
Dynamic Power ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
Layout Area ◽  
And Performance

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

scholarly journals A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1078
Author(s):  
Thi Thuy Pham ◽  
Dongmin Kim ◽  
Seo-Hyeong Jeong ◽  
Junghyup Lee ◽  
Donggu Im
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Supply Voltage ◽  
Current Source ◽  
Low Noise ◽  
The Body ◽  
Common Source ◽  
Conversion Gain ◽  
Input Transistor ◽  
Envelope Detector

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

Sign in / Sign up

Export Citation Format

Share Document