scholarly journals Optimizing the Performance of MOS Stacks

2020 ◽  
Vol 16 (1) ◽  
pp. 85-98
Author(s):  
Sherif Sharroush
Keyword(s):  
Time Delay ◽  
Power Consumption ◽  
Figure Of Merit ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Scaling Factor ◽  
Worst Case ◽  
In Series ◽  
High Transition ◽  
Exclusive Or

CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.

scholarly journals Bus Implementation Using New Low Power PFSCL Tristate Buffers

2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Neeta Pandey ◽  
Bharat Choudhary ◽  
Kirti Gupta ◽  
Ankit Mittal
Keyword(s):  
Power Consumption ◽  
Current Source ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Performance Parameters ◽  
Interesting Consequence ◽  
Spice Simulation ◽  
High Impedance ◽  
Parameter Variations ◽  
Feedback Source

This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.

scholarly journals New Proposal for MCML Based Three-Input Logic Implementation

VLSI Design ◽  
2016 ◽  
Vol 2016 ◽  
pp. 1-10 ◽  
Author(s):  
Neeta Pandey ◽  
Kirti Gupta ◽  
Bharat Choudhary
Keyword(s):  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Concept ◽  
Logic Function ◽  
Circuit Element ◽  
Worst Case ◽  
Xor Gate ◽  
Static Power ◽  
Digital System Design ◽  
Exclusive Or

This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

A Domino Circuit Technique for Noise-Immune High Fan-In Gates

2018 ◽  
Vol 27 (10) ◽  
pp. 1850151 ◽  
Author(s):  
Mohammad Asyaei ◽  
Farshad Moradi
Keyword(s):  
Power Consumption ◽  
Noise Immunity ◽  
Cmos Technology ◽  
Important Concern ◽  
Consumption Reduction ◽  
In Series ◽  
Subthreshold Leakage ◽  
Domino Circuit ◽  
Voltage Swing ◽  
Circuit Technique

Noise immunity is an important concern in deep nano-scale technologies, especially for high fan-in gates. In this paper, a new domino circuit technique is proposed by which the noise immunity of high fan-in gates increases while the power consumption reduces. The proposed technique is based on the comparison of two currents, which vary with respect to the voltage across the pull-down network (PDN). By comparing these currents, the voltage level of the dynamic node is pulled up or pulled down depending on the input voltages. Using this technique, the voltage swing on the PDN can be decreased to reduce the power consumption. Moreover, a diode-connected NMOS transistor is added in series with the PDN in the proposed technique. This will result in reducing the subthreshold leakage current due to the stacking effect and, as a result, the noise immunity will improve. To demonstrate the efficacy of the proposed domino design over the conventional techniques, high fan-in gates are designed and compared in 90[Formula: see text]nm CMOS technology. Simulation results exhibit at least 1.87X noise immunity improvement and 20% power consumption reduction in comparison to the standard footless domino (SFLD) circuits at the same delay.

scholarly journals Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

2020 ◽  
Vol 17 (2) ◽  
pp. 783
Author(s):  
Julie Roslita Rusli ◽  
Suhaidi Shafie ◽  
Roslina Mohd Sidek ◽  
Hasmayadi Abdul Majid ◽  
W. Z. Wan Hassan ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Temperature Variation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Worst Case ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Power Dynamic ◽  
Voltage Supply

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC).  This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed.  The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V.  The method used to verify the robustness of the comparator circuit across 45 PVT is presented.  The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

scholarly journals Design of High Performance Decoder with Mixed Logic Styles

2018 ◽  
Vol 7 (2.20) ◽  
pp. 119
Author(s):  
Mohammad Khadir ◽  
S Renukarani ◽  
Tunikipati Usharani ◽  
D Hemanth Kumar
Keyword(s):  
Time Delay ◽  
Power Consumption ◽  
High Power ◽  
High Performance ◽  
Cmos Technology ◽  
Combinational Circuits ◽  
Framework Design ◽  
Different Types ◽  
Portable Technology ◽  
Low Performance

The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which „n‟ no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transistors to design any MxN decoders using CMOS technology .In order to configure the parameters and to make it more portable we are using different types of logic styles this usage of technologies more than one technologies on each circuit is a mixed logic styles .In this concept we observe the results as per required .The technologies we use in this is TGL/DVL. The suggested framework “Design about low Power, helter execution 2-4 What's more 4-16 blended rationale offering Decoders” is executed done 45nm engineering utilizing cadence virtuoso tool. The circuit schematic is designed and the circuits are simulated for functionality verification.  

scholarly journals A Novel Low-power Shared Division and Square-root Architecture Using the GST Algorithm

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 365-376 ◽  
Author(s):  
Martin Kuhlmann ◽  
Keshab K. Parhi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Root Architecture ◽  
Scale Factor ◽  
Quantitative Comparison ◽  
Scaling Factor ◽  
Square Root ◽  
Worst Case ◽  
Long Time

Although SRT division and square-root approaches and GST division approach have been known for long time, square-root architectures based on the GST approach have not been proposed so far which do not require a final division/multiplication of the scale factor. A GST square-root architecture is developed without requiring either a multiplication to update the scaled square-root quotient in each iteration or a division/multiplication by the scaling factor after completing the square-root iterations. Additionally, quantitative comparison of speed and power consumption of GST and SRT division/square-root units are presented. Shared divider and square-root units are designed based on the SRT and the GST approaches, in minimally and maximally redundant radix-4 representations. Simulations demonstrate that the worst-case overall latency of the minimally-redundant GST architecture is 35% smaller compared to the SRT. Alternatively, for a fixed latency, the minimally-redundant GST architecture based division and square-root operations consume 32% and 28% less power, respectively, compared to the maximally-redundant SRT approach.

DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS

2014 ◽  
Vol 23 (07) ◽  
pp. 1450092 ◽  
Author(s):  
PRABIR SAHA ◽  
DEEPAK KUMAR ◽  
PARTHA BHATTACHARYYA ◽  
ANUP DANDAPAT
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Boolean Logic ◽  
Dynamic Power ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
Layout Area ◽  
And Performance

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

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