Rapid Thermal Processing of III-Nitrides

1997 ◽  
Vol 470 ◽  
Author(s):  
J. Hong ◽  
J. W. Lee ◽  
C. B. Vartuli ◽  
J. D. MacKenzie ◽  
S. M. Donovan ◽  
...  

ABSTRACTTransient thermal processing is employed for implant activation, contact alloying, implant isolation and dehydrogenation during III-nitride device fabrication. We have compared use of InN, AlN and GaN powder as methods for providing a N2 overpressure within a graphite susceptor for high temperature annealing of GaN, InN, A1N and InAlN. The AlN powder provides adequate surface protection to temperatures of ∼1100°C for AlN, > 1050°C for GaN, ∼600°C for InN and ∼800°C for the ternary alloy. While the InN powder provides a higher N2 partial pressure than AlN powder, at temperatures above ∼750°C the evaporation of In is sufficiently high to produce condensation of In droplets on the surfaces of the annealed samples. GaN powder achieved better surface protection than the other two cases.

1985 ◽  
Vol 52 ◽  
Author(s):  
Alwin E. Michel

ABSTRACTTransient enhanced diffusion during rapid thermal processing has been reported for most of the common dopants employed for silicon device fabrication. For arsenic a large amount of the available data is fit by a computational model based on accepted diffusion mechanisms. Ion implanted boron on the other hand exhibits anomalous tails and transient motiou. A time dependence of this displacement is demonstrated at lower temperatures. High temperature rapid anneals are shown to reduce some of the anomalous motion observed for low temperature furnace anneals. A model is described that links the electrical activation with the diffusion and describes both the transient diffusion of rapid thermal processing and the large anomalous diffusion reported many years ago for furnace anneals.


2012 ◽  
Vol 717-720 ◽  
pp. 247-250 ◽  
Author(s):  
Bernd Zippelius ◽  
Jun Suda ◽  
Tsunenobu Kimoto

In this paper the impact of high temperature annealing on the formation of intrinsic defects in 4H-SiC such as Z1/2 and EH6/7 was examined. Therefore, three epitaxial layers with various initial concentrations of the Z1/2- and EH6/7-centers (1011 – 1013 cm-3) were investigated. It turns out that depending on the initial defect concentration the high temperature annealing leads to a monotone increase of the Z1/2- and EH6/7-concentration in a temperature range from 1600 to 1750°C. For a defined temperature above these values, the resulting defect concentration is independent of the sample’s initial values. Beside the growth conditions themselves such as C/Si ratio the thermal post-growth processing has a severe impact on the carrier lifetime which must be taken into account during device fabrication.


1988 ◽  
Vol 144 ◽  
Author(s):  
F. K. Yang ◽  
S. J. Pien ◽  
R. Kwor

ABSTRACTA thermal analysis is performed to simulate the rapid heating process for ion implanted GaAs with consideration of the doping effect. The results are for cases with various concentrations and thicknesses of doping layer. Also studied are the heating processes for silicon dioxide capped GaAs. The effects of the thickness of the oxide layer are discussed. The magnitude of the temperature differences across the wafer is addressed. The present analysis considers xenon-arc lamps and tungsten-halogen lamps as the light sources.


1993 ◽  
Vol 317 ◽  
Author(s):  
John E. Manan ◽  
Robert G. Long ◽  
André Vantomme ◽  
Marc-A. Nicolet

ABSTRACTThe template growth technique was applied to the growth of CrSi2 thin films on Si(111) by UHV E-gun evaporation. A 4He+ channeling yield of -50% was obtained for an epitaxial -2100 Å-thick film of continuous morphology grown at 450° C The heteroepitaxial relationship is CrSi2 (001) / Si (lll) with CrSi2[210] ∥ Si<110>.In the case of film formation simply via reactive deposition epitaxy (RDE, chromium evaporation onto hot substrates) a severe crystallinity-Morphology tradeoff is always observed. Continuous films are formed at low temperature but no long-range epitaxy is found. On the other hand, high temperature annealing of these films induces the formation of islands that show good epitaxial alignment with the substrate. This tradeoff was addressed with the template growth technique.


1996 ◽  
Vol 429 ◽  
Author(s):  
P. J. Timans

AbstractRapid thermal processing (RTP) has become a key technology in the fabrication of advanced semiconductor devices. As RTP becomes the accepted technique for an increasingly wide range of processes in device fabrication, the understanding of the basic physics of radiation heat transfer in RTP systems is also being extended rapidly. This paper illustrates the use of optical models for prediction of the thermal radiative properties of semiconductor wafers. Such calculations can be used to address many of the key issues of interest in RTP, including questions concerning temperature measurement and process repeatability.


1990 ◽  
Vol 202 ◽  
Author(s):  
C. S. Galovich ◽  
S. S. Lee ◽  
D. L. Kwong

ABSTRACTTitanium nitride, formed either by rapid thermal processing (RTP) or reactive sputtering, is commonly applied as a barrier film in the fabrication of metal-to-substrate contacts for CMOS devices. In one approach a titanium film is sputtered onto a patterned dielectric and then nitrided at a temperature greater than 500° C to form a TiN layer. Variations in the structure and resistivity of the titanium layer are observed when the titanium overlies a borophosphosilicate glass (BPSG) film. The structural change appears as a “wrinkling” of the TiN film and the TiN/BPSG interface. More severely wrinkled films are characterized by lower sheet resistivities. Results of TEM and SEM analyses are presented, as well as data on TiN resistivity and reflectance for nitridation temperatures in the range 650°C to 900°C, and for BPSG boron and phosphorus concentrations of approximately 3 to 5 wt. %. Mechanisms for the TiN wrinkling are discussed.


2007 ◽  
Vol 1012 ◽  
Author(s):  
Immo Michael Kötschau ◽  
Humberto Rodriguez-Alvarez ◽  
Cornelia Streeck ◽  
Alfons Weber ◽  
Manuela Klaus ◽  
...  

AbstractThe rapid thermal processing (RTP) of Cu-rich Cu/In precursors for the synthesis of CuInS2 thin films is possible within a broad processing window regarding leading parameters like top temperature, heating rate, and Cu excess. The key reaction pathway for the CuInS2 phase formation has already been investigated by in-situ energy dispersive X-ray diffraction (EDXRD) for various precursor stoichiometries, heating rates and top temperatures at sulphur partial pressure conditions which are typical for physical vapour deposition processes. According to the phase diagrams of the binary sulphide phases, the sulfur partial pressure strongly determines the occuring crystalline phases. However, a controlled variation of the maximum sulphur partial in a typical RTP experiment has not been carried out yet. In order to study the influence of this parameter a special RTP reaction chamber was designed suitable for in-situ EDXRD experiments at the EDDI beamline at BESSY, Berlin. In a typical in-situ RTP/EDXRD experiment sulphur and a Cu/In/Mo/glass precursor are placed in an evacuated graphite reactor. The amount of sulphur determines the maximum pressure available at the top temperature of the experiment. As the RTP process proceeds a complete EDXRD spectrum is acquired every 10 seconds and thus the various stages of the reaction path and the crystalline phases can be monitored. The first experiments show already a significant change in the reaction pathway and the secondary Cu-S phases which segregate on top of the CuInS2 thin film during the reaction.


1997 ◽  
Vol 470 ◽  
Author(s):  
H. Gilboa ◽  
Y. E. Gilboa ◽  
Z. Atzmon ◽  
S. Levy ◽  
H. Spilberg ◽  
...  

ABSTRACTThe evolution of integrated single-wafer processing for high-temperature applications in the front end of the line (FEOL) occurred with the advancements in single-wafer rapid thermal processing and its acceptance as a manufacturing technology. The Integra RTCVD cluster tool for high-temperature applications features wafer cleaning, rapid thermal processing and single wafer chemical vapor deposition steps. The paper presents integrated vapor phase clean and RTCVD applications for FLASH memory gate stack and DRAM cell.


Author(s):  
S. J. Krause ◽  
C. O. Jung ◽  
S.R. Wilson

Silicon-on-insulator (SOI) structure by high dose oxygen implantation (SIMOX) has excellent potential for use in radiation hardened and high speed integrated circuits. Device fabrication in SIMOX requires a high quality superficial Si layer above the buried oxide layer. Previously we reported on the effect of heater temperature, background doping, and annealing cycle on precipitate size, density, and location in the superficial Si layer. Precipitates were not eliminated with our processing conditions, but various authors have recently reported that high temperature annealing of SIMOX, from 1250°C to 1405°C, eliminates virtually all precipitates in the superficial Si layer. However, in those studies there were significant differences in implantation energy and dose and also annealing time and temperature. Here we are reporting on the effect of annealing time and temperature on the formation and changes in precipitates.


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