Frequency Sensitive Soft Fails in SRAM Arrays

2010 ◽  
Author(s):  
Sweta Pendyala ◽  
Terence Kane ◽  
Michael Tenney ◽  
Richard Oldrey ◽  
Manuel Villalobos ◽  
...  
Keyword(s):  
Paradigm Shift ◽  
Capacitance Measurement ◽  
Physical Analysis ◽  
Voltage Measurement ◽  
Electrical Measurements ◽  
Root Cause ◽  
Atomic Force ◽  
Capacitance Voltage ◽  
First Time

Abstract Root cause analysis of frequency sensitive “soft” failures in SRAM arrays pose unusual challenges to the failure analyst. Conventional atomic force probe (AFP) DC measurements cannot reliably identify the failure source. The employment of tester based schmoo screening have been shown to correlate with AFP AC quantitative capacitance measurements for the first time. The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for localization has been previously described [1,2,3]. By exploiting the dC/dV component of the NCVS signal shown in Figure 1 and integrating this output, a quantitative capacitance versus voltage measurement can be demonstrated. This quantitative capacitance measurement identified a frequency sensitve horizontal pair failure (HPF) in the SRAM array. Subsequent process vintage analysis identified the source and eliminated these frequency sensitive HPF characterisics. Given the sensitive nature of these fails, conventional physical analysis methods of TEM EELS, and cross section scanning capacitance analysis were not successful in finding the root cause. This underlies a paradigm shift in failure analysis. Electrical measurements may be the only means to identify a process problem and follow-up process vintage analysis is required to solution the root cause.

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

Wafer Level Atomic Force Probing

2010 ◽  
Author(s):  
Terence Kane ◽  
Sweta Pendyala ◽  
Michael P. Tenney
Keyword(s):  
Silicon On Insulator ◽  
Wafer Level ◽  
Access Memory ◽  
Laboratory Practice ◽  
Deep Trench ◽  
Atomic Force ◽  
Capacitance Voltage ◽  
First Time ◽  
Process Level ◽  
Insight Into

Abstract The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1,2,3]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) on bulk silicon wafers and silicon on insulator (SOI) wafers to characterize discrete MOSFET and SOI embedded dynamic ramdom access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy has also been highlighted [1,2,3,4,5,6]. Typically, this laboratory AFP characterization is employed on die fragments sampled from whole wafers following back end of the line (BEOL) metallization processing and test. The process vintage of this hardware can be as much as three months after the critical FEOL processing has occurred. This paper is intended to describe for the first time the methodology of applying AFP on whole 300mm wafers at the post CA chemical-mechanical polishing (CMP) process level to provide a real time insight into yield issues that would not be detected until subsequent BEOL metallization processing and testing. This new AFP tool incorporates enhanced features enabling both DC measurements as well as AC capacitance voltage measurements of discrete deep trench embedded DRAM (eDRAM) devices for 32nm, 28nm, and 20nm node technologies.

Ferroelectric Behavior of Li-Doped ZnO Thin Films on Si(100) by Pulsed Laser Deposition

1998 ◽  
Vol 541 ◽  
Author(s):  
M. Joseph ◽  
H. Tabata ◽  
T. Tkawai
Keyword(s):  
Thin Films ◽  
Pulsed Laser Deposition ◽  
Pulsed Laser ◽  
Laser Deposition ◽  
Zno Thin Films ◽  
Voltage Measurement ◽  
Capacitance Voltage ◽  
Structural Surface ◽  
Doped Zno ◽  
First Time

AbstractThin films of Li-doped ZnO of different compositions (Zn1−xLix)O, x=0.1, 0.17 and 0.3 have been prepared on Si(100) substrate for the first time by pulsed laser deposition. These films are characterized for their structural, surface morphology and ferroelectric nature. A memory window of 1.2V has been observed in capacitance-voltage measurement.

Psychological Resilience Provides No Independent Protection From Suicidal Risk

Crisis ◽  
2016 ◽  
Vol 37 (2) ◽  
pp. 130-139 ◽  
Author(s):  
Danica W. Y. Liu ◽  
A. Kate Fairweather-Schmidt ◽  
Richard Burns ◽  
Rachel M. Roberts ◽  
Kaarin J. Anstey
Keyword(s):  
Risk Factors ◽  
Well Being ◽  
Current Status ◽  
Psychological Resilience ◽  
Cross Sectional ◽  
Life Project ◽  
Resilience Factors ◽  
First Time

Abstract. Background: Little is known about the role of resilience in the likelihood of suicidal ideation (SI) over time. Aims: We examined the association between resilience and SI in a young-adult cohort over 4 years. Our objectives were to determine whether resilience was associated with SI at follow-up or, conversely, whether SI was associated with lowered resilience at follow-up. Method: Participants were selected from the Personality and Total Health (PATH) Through Life Project from Canberra and Queanbeyan, Australia, aged 28–32 years at the first time point and 32–36 at the second. Multinomial, linear, and binary regression analyses explored the association between resilience and SI over two time points. Models were adjusted for suicidality risk factors. Results: While unadjusted analyses identified associations between resilience and SI, these effects were fully explained by the inclusion of other suicidality risk factors. Conclusion: Despite strong cross-sectional associations, resilience and SI appear to be unrelated in a longitudinal context, once risk/resilience factors are controlled for. As independent indicators of psychological well-being, suicidality and resilience are essential if current status is to be captured. However, the addition of other factors (e.g., support, mastery) makes this association tenuous. Consequently, resilience per se may not be protective of SI.

Silicon Surface Chemical Treatments in Oxide/Nitride Dielectric Stack Properties

2002 ◽  
Vol 716 ◽  
Author(s):  
D. Jacques ◽  
S. Petitdidier ◽  
J.L. Regolini ◽  
K. Barla
Keyword(s):  
Oxygen Content ◽  
Oxide Thickness ◽  
Morphological Data ◽  
Electrical Characteristics ◽  
Electrical Measurements ◽  
Chemical Cleaning ◽  
Force Microscopy ◽  
Chemical Treatments ◽  
Atomic Force ◽  
Interfacial Oxygen

AbstractOxide/Nitride dielectric stack is widely used as the standard dielectric for DRAM capacitors. The influence of the chemical cleaning prior to the stack formation has been studied in this work. As a result, morphological data such as stack surface roughness (Atomic Force Microscopy) and silicon nitride (SiN) incubation time for growth are comparable for all the studied cases on <Si>. However, Tof-SIMS exhibits different oxygen content at the Si/stack interface following the different chemical treatments. Electrical measurements show comparable C-V and I-V results, for the same Equivalent Oxide Thickness (same capacitance at strong accumulation i.e.-3V) while the different studied interfaces bring different interface states density with lower values for higher interfacial oxygen content. For DRAM applications, a clear improvement in electrical characteristics is obtained under low interfacial oxygen content conditions. Results are compared in embedded-DRAM cells for which we developed an industrially compatible dielectric deposition sequence to obtain minimum leakage current with maximum specific capacitance and no particular linking constraints.

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Marginal RF Gain Investigation and Root Cause Determination

2013 ◽  
Author(s):  
Keith Harber ◽  
Steve Brockett
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Power Amplifier ◽  
Physical Analysis ◽  
Root Cause ◽  
S Parameter ◽  
Mode Of Operation ◽  
S Parameters

Abstract This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.

Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

2000 ◽  
Author(s):  
J. N. C. de Luna ◽  
M. O. del Fierro ◽  
J. L. Muñoz
Keyword(s):  
Flash Memory ◽  
Electromagnetic Interference ◽  
Yield Loss ◽  
High Amplitude ◽  
Physical Analysis ◽  
Input Buffer ◽  
Automated Test Equipment ◽  
Root Cause ◽  
Root Cause Identification ◽  
Test Process

Abstract An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.

Analysis of Induced End-of-Life Failures in SRAM Through Nanoprobing

2018 ◽  
Author(s):  
Oberon Dixon-Luinenburg ◽  
Jordan Fine
Keyword(s):  
End Of Life ◽  
Soft Errors ◽  
Cause Analysis ◽  
New Approach ◽  
Performance Loss ◽  
Root Cause ◽  
Long Period ◽  
Atomic Force ◽  
Stress Resultant ◽  
Voltage Stress

Abstract In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.

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