An Effective Failure Analysis Strategy for the Successful Introduction of New Products Designed in 90 and 65 nm CMOS Technologies

2004 ◽  
Author(s):  
F. Lorut ◽  
M. Lamy ◽  
M. de la Bardonnie ◽  
S. Fabre ◽  
R. Ross ◽  
...  
Keyword(s):  
Failure Analysis ◽  
New Products ◽  
Fault Isolation ◽  
Physical Characterization ◽  
Parametric Test ◽  
Process Improvements ◽  
Characterization Techniques ◽  
Analysis Strategy ◽  
Voltage Contrast

Abstract IC manufacturers, among other things, have to define a global failure analysis (FA) strategy that is best adopted to the challenges associated to the introduction of the 90 and 65 nm CMOS technologies. This article reviews the existing FA techniques and then describes an FA strategy that is aiming at fast, efficient, and economic learning in the latest 120-65 nm CMOS technologies. The strategy is based on a well-balanced mix and usage of in-line defectivity data, voltage contrast analyses, SRAM bitmap analysis results, OBIRCH fault isolation, and various advanced physical characterization techniques. A SRAM bitmap strategy has demonstrated to be very effective in driving most relevant process improvements, and also OBIRCH applied to parametric test structures has helped significantly in identifying major yield detractors.

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

2003 ◽  
Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Fault Isolation ◽  
Electronic Information ◽  
Scan Testing ◽  
Challenging Environment ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Higher Sensitivity

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Effective and Efficient FEOL Defects Localization/Inspection by Selective Mechanical/Chemical Deprocessing

2014 ◽  
Author(s):  
Ng Hui Peng ◽  
Teo Angela ◽  
Ang Ghim Boon ◽  
Yip Kim Hong ◽  
Chang Qing Chen ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Spatial Resolution ◽  
Rapid Development ◽  
Plasma Chemistry ◽  
Fault Isolation ◽  
Physical Analysis ◽  
Process Improvements ◽  
Front End ◽  
Manufacturing Technologies ◽  
Device Miniaturization

Abstract With the rapid development of semiconductor manufacturing technologies, IC devices evolve to smaller feature sizes and higher densities, and thus the task of performing successful failure analysis (FA) is becoming increasingly difficult. Device miniaturization often requires high spatial resolution fault isolation and physical analysis [1]. To cater to the shrinking of devices, extensive process improvements have been conducted at the front-end-of-line (FEOL) structures. As a result, among the numerous types of defects leading to chip failure, FEOL defects are becoming more common for devices of advanced tech nodes [2]. Therefore, it becomes more complexity and difficulty on searching the physical defect. Sample preparation is a key activity in material and failure analysis. In order to image small structures or defects it is often necessary to remove excess material or layers hiding the feature of interest. Removing selected layers to isolate a structure is called delayering. It can be accomplished by chemical etching using liquid or plasma chemistry, or by mechanical means, by polishing off each unwanted layer.

Process Flow Employed for Parametric Test Structure Chain Opens Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2016 ◽  
Author(s):  
Satish Kodali ◽  
Yinzhe Ma ◽  
Chong Khiam Oh ◽  
Wayne Zhao ◽  
Felix Beaudoin
Keyword(s):  
Cross Sections ◽  
Process Development ◽  
Fault Isolation ◽  
Flow Sheet ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Voltage Contrast ◽  
Root Cause Identification ◽  
20 Nm

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of a line. This work provides a process flow sheet for root cause identification on chain opens on advanced 20 nm and sub-20 nm technologies setting a standard guideline for a specific category fail type. It provides a consistent way of attack in a much more streamlined fashion. Further, dependability on TEM rather than convention FIB cross-sections provides shortest time to root cause identification. Three typical cases encountered are discussed to demonstrate the idea: embedded chain opens by electron beam absorbed current (EBAC) isolation, chains opens at level by EBAC isolation, and chains opens at level by passive voltage contrast isolation.

Stacked Polysilicon/Metal Capacitors Failure Analysis

2005 ◽  
Author(s):  
Dat T. Nguyen ◽  
Frank Huang
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Visual Defect ◽  
Capacitor Plate ◽  
Chemical Etch ◽  
Defect Localization ◽  
Voltage Contrast

Abstract Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.

Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

2017 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Cmos Technology ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Conductive Atomic Force Microscopy ◽  
Isolation Technique ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Atomic Force ◽  
Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Rapid Failure Analysis of Low-Yielding Electrical Test Structures Using E-beam Physical and Voltage Contrast Inspection

2013 ◽  
Author(s):  
Oliver D. Patterson ◽  
Deborah A. Ryan ◽  
Xiaohu Tang ◽  
Shuen Cheng Lei
Keyword(s):  
Failure Analysis ◽  
Defect Detection ◽  
High Volume ◽  
The Other ◽  
Defect Inspection ◽  
Electrical Test ◽  
Detection Mode ◽  
Rapid Generation ◽  
Voltage Contrast ◽  
Additional Support

Abstract In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

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