scholarly journals A High Speed Latched Circuit for Flash ADC

2019 ◽  
Vol 8 (12) ◽  
pp. 3741-3745
Keyword(s):  
Integrated Circuit ◽  
Continuous Time ◽  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Time Varying ◽  
Slew Rate ◽  
Digital Signals ◽  
Flash Adc ◽  
Offset Voltage

Practically all electronic systems are realized using integrated circuit(IC) chips. The IC design requires digital signals, but however the physical signals available routinely are either continuous time varying signals or corrupted discrete voltages. These continuous time varying input signals are converted to full voltage swing digital signals by means of a comparator circuit. The comparators use regenerative feedback to transform the output to a full scale digital signal. The core specifications considered in this comparator implementation are power dissipation (PD), propagation delay (tP), output offset voltage and slew rate. The circuit is simulated in CMOS 180nm technology using Tanner EDA tool. The high speed latched comparator circuit is powered with a 1.8V DC power supply and the obtained results show that it operates at 1.67GHz, slew rate is 126 V/µS and the dynamic power dissipation is found to be 0.328mW.

DESIGNING OF ALL-OPTICAL TRI-STATE LOGIC SYSTEM WITH THE HELP OF OPTICAL NONLINEAR MATERIAL

2008 ◽  
Vol 17 (03) ◽  
pp. 315-328 ◽  
Author(s):  
TANAY CHATTOPADHYAY ◽  
GOUTAM KUMAR MAITY ◽  
JITENDRA NATH ROY
Keyword(s):  
High Speed ◽  
Optical Switch ◽  
Digital Signal ◽  
Optical Signal ◽  
Nonlinear Material ◽  
Digital Signals ◽  
Photonic Networks ◽  
Optical Nonlinear Material ◽  
All Optical ◽  
Logic Operations

Nonlinear optics has been of increased interest for all-optical signal, data and image processing in high speed photonic networks. The application of multi-valued (nonbinary) digital signals can provide considerable relief in transmission, storage and processing of a large amount of information in digital signal processing. Here, we propose the design of an all-optical system for some basic tri-state logic operations (trinary OR, trinary AND, trinary XOR, Inverter, Truth detector, False detector) which exploits the polarization properties of light. Nonlinear material based optical switch can play an important role. Tri-state logic can play a significant role towards carry and borrow free arithmetic operations. The principles and possibilities of the design of nonlinear material based tri-state logic circuits are proposed and described.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

2014 ◽  
Vol 573 ◽  
pp. 187-193 ◽  
Author(s):  
Anitha Ponnusamy ◽  
Palaniappan Ramanathan
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
High Speed ◽  
Total Power ◽  
Single Chip ◽  
Flip Flop ◽  
Design And Optimization ◽  
Negative Edge ◽  
Carry Select Adder ◽  
Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

scholarly journals High Speed PSO Micro-Pipelined Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 4073-4079
Keyword(s):  
Digital Signal Processor ◽  
Power Dissipation ◽  
High Speed ◽  
Continuous Monitoring ◽  
Digital Signal ◽  
Propagation Delay ◽  
Wearable Devices ◽  
Data Path ◽  
Processing Data ◽  
Cost Utilization

For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.

scholarly journals Matched Filter Based Detection over Time Varying Fading Channels with Reduced Complexity

2019 ◽  
pp. 1-6
Author(s):  
Mohd Israil
Keyword(s):  
Signal Processing ◽  
Maximum Likelihood ◽  
Fading Channels ◽  
High Speed ◽  
Matched Filter ◽  
Signal To Noise Ratio ◽  
Digital Signal ◽  
Time Varying ◽  
High Speed Data ◽  
Over Time

Challenges in high speed data transmission technology over time varying fading channels is addressed in this paper. More precisely, the signal processing at the receiver side has to be analyzed for such systems, as it is well known that the mobile radio channels are characterized by frequency selective fast fading is typically introduced error in the received signal. Thus, the performance of the receiver severely degraded because of such factors. Specifically, this paper deals with the detection using a matched filter followed by low weight near maximum likelihood detector (NMLD) for the application of digital signal processing in outdoor vehicular radio environments. Nearly Maximum Likelihood Detection depends on the length of the stored vectors as well as depends on the numbers of the stored vector. In [1] complexity is reduced by reducing the stored vectors, in this paper same NMLD used but the complexity of the matched filter is reduced by some variance. Finally, the bit error rate (BER) is measured with signal to noise ratio.

scholarly journals Automated Metabolic P System Placement in FPGA

2016 ◽  
Vol 10 (1) ◽  
pp. 5-12 ◽  
Author(s):  
Darius Kulakovskis ◽  
Dalius Navakauskas
Keyword(s):  
Integrated Circuit ◽  
Code Generation ◽  
Digital Signal Processor ◽  
High Speed ◽  
Digital Signal ◽  
Intravenous Glucose Tolerance Test ◽  
Photochemical Quenching ◽  
P System ◽  
Final Decision ◽  
Intravenous Glucose

Abstract An original Very High Speed Integrated Circuit Hardware Description Language (VHDL) code generation tool that can be used to automate Metabolic P (MP) system implementation in hardware such as Field Programmable Gate Arrays (FPGA) is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT), and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP), slice, and 4-input LUT usage.

scholarly journals Implementation of Audio Effect Generator in FPGA

2015 ◽  
Vol 15 (1) ◽  
pp. 89-98
Author(s):  
Sujit Rokka Chhetri ◽  
Bikash Poudel ◽  
Sandesh Ghimire ◽  
Shaswot Shresthamali ◽  
Dinesh Kumar Sharma
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Mathematical Formulation ◽  
Digital Signal ◽  
Ip Core ◽  
Field Programmable ◽  
Ip Cores ◽  
Shift Effect ◽  
Effect Generator ◽  
Pitch Shift

This paper describes the theory and implementation of audio effects such as echo, distortion and pitch-shift in Field Programmable Gate Array (FPGA). At first the mathematical formulation for generation of such effects is explained and then the algorithm is described for its implementation in FPGA using Very high speed integrated circuit hardware descriptive language (VHDL). The digital system being designed, which is synthesizable and reconfigurable, offers a great flexibility and scalability in designing and prototyping in FPGAs. The system is divided into three HDL blocks, each for echo, distortion, and pitch-shift effect generation, which are multiplexed in order to share the common ADC and DAC. The audio effect generator designed in this paper was successfully implemented in Spartan-3E FPGA utilizing the resources available effectively. There has been tremendous research being carried out in the field of IP core. Efficient IP cores designed to carry out digital signal processing are implemented in every modern device using configurable logics. This trend hasn’t yet been realized in Nepal. Through the design and implementation of audio effect generator, this paper also aims at bringing the field of IP core development to limelight among scholars of Nepal.DOI: http://dx.doi.org/10.3126/njst.v15i1.12022 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 89-98

HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY

2003 ◽  
Vol 13 (01) ◽  
pp. 221-237
Author(s):  
KARL E. FRITZ ◽  
BARBARA A. RANDALL ◽  
GREGG J. FOKKEN ◽  
MICHAEL J. DEGERSTROM ◽  
MICHAEL J. LORSUNG ◽  
...  
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Silicon Germanium ◽  
High Speed ◽  
Digital Signal ◽  
Electronic Warfare ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Military Systems

Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

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