A Comparison Study of Three of Input Buffer Designed Using 0.35µm CMOS Technology

2013 ◽  
Vol 646 ◽  
pp. 184-190
Author(s):  
Shinta Kisriani ◽  
Eri Prasetyo Wibowo ◽  
Busono Soerowirdjo ◽  
Hamzah Afandi ◽  
Veronica Ernita Kristianti
Keyword(s):  
Input Signal ◽  
Delay Time ◽  
Digital Signal ◽  
Cmos Technology ◽  
Memory Device ◽  
Comparison Study ◽  
Comparison Analysis ◽  
Input Buffer ◽  
Technology Analysis ◽  
Parallel Input

In memory device that is contained in the digital application, there is a sequence of input buffer.The input buffer’s function is to improve a digital signal and remove noise. The buffer circuit take these input signal with imperfections and convert them in to full digital logic levels by slicing the signals at correct levels which depends upon the switching point voltage. In this paper,using three topologies, that are NMOS, PMOS and Parallel input buffer. It would be present into design, simulation and analysis of all topologies input buffer. The result in this paper to determine the best of the three topologies to used. The delay time used to determine the best of topologies. Mentor graphic is tools which used in this paper to design and simulation. The technology used in this paper is 0.35 µm CMOS Technology. Analysis of comparison all of topologies used in this paper based on six parameters. The result of comparison analysis can be seen in more details in this explanation.

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

2016 ◽  
Vol 25 (08) ◽  
pp. 1650084 ◽  
Author(s):  
Liang Zhang ◽  
Dengquan Li ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Common Source ◽  
Digital Converter ◽  
Input Buffer ◽  
Analog To Digital ◽  
Source Follower ◽  
Time Interleaved

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

scholarly journals A Comparison Study on Multilayered Barrier Oxide Structure in Charge Trap Flash for Synaptic Operation

Crystals ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 70
Author(s):  
Minkyung Kim ◽  
Eunpyo Park ◽  
In Soo Kim ◽  
Jongkil Park ◽  
Jaewook Kim ◽  
...  
Keyword(s):  
Memory Device ◽  
Spike Timing ◽  
Comparison Study ◽  
Oxide Structure ◽  
Charge Trap ◽  
Synaptic Functions ◽  
Essential Components ◽  
Neuromorphic System ◽  
A Charge ◽  
Synaptic Operation

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS2 channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al2O3 and SiO2) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.

scholarly journals 3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 598
Author(s):  
Jean-François Pratte ◽  
Frédéric Nolet ◽  
Samuel Parent ◽  
Frédéric Vachon ◽  
Nicolas Roy ◽  
...  
Keyword(s):  
Large Scale ◽  
Single Photon ◽  
Time Of Flight ◽  
Digital Signal ◽  
Liquid Argon ◽  
Cmos Technology ◽  
System Level ◽  
Superior Performance ◽  
Digital Converter ◽  
Positron Emission

Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications. However, multiple applications require greater performance than the current SiPMs are capable of, for example timing resolution for time-of-flight positron emission tomography and time-of-flight computed tomography, and mitigation of the large output capacitance of SiPM array for large-scale time projection chambers for liquid argon and liquid xenon experiments. In this contribution, the case will be made that 3D photon-to-digital converters, also known as 3D digital SiPMs, have a potentially superior performance over analog and 2D digital SiPMs. A review of 3D photon-to-digital converters is presented along with various applications where they can make a difference, such as time-of-flight medical imaging systems and low-background experiments in noble liquids. Finally, a review of the key design choices that must be made to obtain an optimized 3D photon-to-digital converter for radiation instrumentation, more specifically the single-photon avalanche diode array, the CMOS technology, the quenching circuit, the time-to-digital converter, the digital signal processing and the system level integration, are discussed in detail.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

scholarly journals Improved Stability and Controllability in ZrN-Based Resistive Memory Device by Inserting TiO2 Layer

Micromachines ◽  
2020 ◽  
Vol 11 (10) ◽  
pp. 905
Author(s):  
Junhyeok Choi ◽  
Sungjun Kim
Keyword(s):  
Data Storage ◽  
Resistive Switching ◽  
Memory Device ◽  
Comparison Study ◽  
Tio2 Layer ◽  
Bipolar Resistive Switching ◽  
Resistive Switching Memory ◽  
Current Voltage ◽  
Improved Stability ◽  
Switching Characteristics

In this work, the enhanced resistive switching of ZrN-based resistive switching memory is demonstrated by embedding TiO2 layer between Ag top electrode and ZrN switching layer. The Ag/ZrN/n-Si device exhibits unstable resistive switching as a result of the uncontrollable Ag migration. Both unipolar and bipolar resistive switching with high RESET current were observed. Negative-SET behavior in the Ag/ZrN/n-Si device makes set-stuck, causing permanent resistive switching failure. On the other hand, the analogue switching in the Ag/TiO2/ZrN/n-Si device, which could be adopted for the multi-bit data storage applications, is obtained. The gradual switching in Ag/TiO2/ZrN/n-Si device is achieved, possibly due to the suppressed Ag diffusion caused by TiO2 inserting layer. The current–voltage (I–V) switching characteristics of Ag/ZrN/n-Si and Ag/TiO2/ZrN/n-Si devices can be well verified by pulse transient. Finally, we established that the Ag/TiO2/ZrN/n-Si device is suitable for neuromorphic application through a comparison study of conductance update. This paper paves the way for neuromorphic application in nitride-based memristor devices.

scholarly journals Low power and high speed GDI based convolution using Vedic multiplier

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Basic Building Block ◽  
Extensive Area ◽  
Vedic Multiplier

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 

Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length

1996 ◽  
Vol 8 (6) ◽  
pp. 524-530
Author(s):  
Yoshichika Fujioka ◽  
◽  
Nobuhiro Tomabechi
Keyword(s):  
Feedback Control ◽  
Visual Feedback ◽  
Digital Signal Processor ◽  
Delay Time ◽  
Word Length ◽  
Data Transfer ◽  
Digital Signal ◽  
Parallel Processor ◽  
Intelligent Robots ◽  
Visual Feedback Control

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multioperand multiply-additions. To reduce the delay time for the multiply-additions, switch circuit is used to change the direct connection between the multipliers and adders, so that the overhead in data transfer is reduced. To change the word-length of the multi-operand multiply-adders, in addition, the switches are also provided in multipliers and adders. By changing to the short wordlength, the numbers of multiplier and adders can be increased. The performance evaluation shows that the delay time for visual feedback control becomes about 6 times faster than that of a parallel processor approach using conventional digital signal processor (DSPs).

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

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