The bifurcation of advanced packaging

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000834-000855
Author(s):  
John Park
Keyword(s):  
Printed Circuit Board ◽  
Mechanical Design ◽  
Design Tool ◽  
Circuit Board ◽  
Design Tools ◽  
Wafer Level ◽  
3D Ic ◽  
Package Design ◽  
The Past ◽  
Advanced Packaging

Following a similar trend from the 1990's, IC package design is experiencing a sea change. As a refresher, the 1990's is when the ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of the BGA. In short, the BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. On top of that, IO's were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs. As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved! Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace, are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking and, in some cases, chips being packaged directly at the wafer-level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like, 2.5D/3D IC and fan-out wafer-level packaging (FOWLP). Instead, in all likelihood IC design tools and flows will need to be slightly adapted to support the next generation of package designs. Let's start with foundry-based FOWLP. In this case, induvial dice are placed on a chip-carrier with additional spacing between them. Molding is poured in the empty space and then an array of bumps (UBM) and the connectivity (RDL) are added. In foundry-based flows, these UBM and RDL layers require IC-styled routing/metal fill and mask generation from the layout tool. In addition, these masks must be verified with traditional IC DRC/LVS tools. It's clear that some kind of hybrid advanced packaging flow using some traditional IC tools in the flow is required to support this type of design. And in fact, if you look at the largest semiconductor foundries reference flow tools, you will find this to be true. This presentation further examines the design tool/flow requirement for FOWLP, 2.5D/3D IC and future multi-die packaging technologies.

Validation of the Critical Strain-Based Methodology for Evaluating the Mechanical Safety of Ball Grid Array Solder Joints in a Launch Random Vibration Environment

2021 ◽  
Author(s):  
Tae-Yong Park ◽  
Hyun-Ung Oh
Keyword(s):  
Fatigue Life ◽  
Random Vibration ◽  
Critical Strain ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mechanical Design ◽  
Ball Grid Array ◽  
Primary Objective ◽  
Circuit Board ◽  
Analytical Approaches

Abstract To overcome the theoretical limitations of Steinberg's theory for evaluating the mechanical safety of the solder joints of spaceborne electronics in a launch random vibration environment, a critical strain-based methodology was proposed and validated in a previous study. However, for the critical strain-based methodology to be used reliably in the mechanical design of spaceborne electronics, its effectiveness must be validated under various conditions of the package mounting locations and the first eigenfrequencies of a printed circuit board (PCB); achieving this validation is the primary objective of this study. For the experimental validation, PCB specimens with ball grid array packages mounted on various board locations were fabricated and exposed to a random vibration environment to assess the fatigue life of the solder joint. The effectiveness of the critical strain-based methodology was validated through a comparison of the fatigue life of the tested packages and their margin of safety, which was estimated using various analytical approaches.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000325-000330 ◽  
Author(s):  
Wei Zhao ◽  
Mark Nakamoto ◽  
Karthikeyan Dhandapani ◽  
Brian Henderson ◽  
Ron Lindley ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measured Data ◽  
Circuit Board ◽  
Wafer Level ◽  
Test Chip ◽  
Chip Design ◽  
Packaging Technology ◽  
Printed Circuit ◽  
Wafer Level Packaging ◽  
Simulation Results

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

Thermal Performance of Microelectronic Substrates With Submillimeter Integrated Vapor Chamber

2019 ◽  
Vol 141 (5) ◽  
Author(s):  
Sangbeom Cho ◽  
Yogendra Joshi
Keyword(s):  
Heat Transfer ◽  
Thermal Performance ◽  
Printed Circuit Board ◽  
Mechanical Design ◽  
Three Dimensional ◽  
Circuit Board ◽  
Working Fluid ◽  
Vapor Chamber ◽  
Conduction Model ◽  
Printed Circuit

We develop a vapor chamber integrated with a microelectronic packaging substrate and characterize its heat transfer performance. A prototype of vapor chamber integrated printed circuit board (PCB) is fabricated through successful completion of the following tasks: patterning copper micropillar wick structures on PCB, mechanical design and fabrication of condenser, device sealing, and device vacuuming and charging with working fluid. Two prototype vapor chambers with distinct micropillar array designs are fabricated, and their thermal performance tested under various heat inputs supplied from a 2 mm × 2 mm heat source. Thermal performance of the device improves with heat inputs, with the maximum performance of ∼20% over copper plated PCB with the same thickness. A three-dimensional computational fluid dynamics/heat transfer (CFD/HT) numerical model of the vapor chamber, coupled with the conduction model of the packaging substrate is developed, and the results are compared with test data.

scholarly journals Effective Strategies for Project-Based Learning of Practical Electronics

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2245
Author(s):  
Faisal Mohd-Yasin
Keyword(s):  
Undergraduate Students ◽  
Printed Circuit Board ◽  
Evaluation Criteria ◽  
Project Based Learning ◽  
Circuit Board ◽  
Learning And Teaching ◽  
Effective Strategies ◽  
The Past ◽  
Component Selection ◽  
Learning Institutions

Some universities offer specific project-based learning (PBL) courses in the third year of their electronic engineering degree to equip undergraduate students before they embark on industrial attachment and/or a capstone project. This course exposes those students to full design cycles at circuit and system levels. Students also pick up practical skills, such as component selection, circuit troubleshooting, printed circuit board design, and market analysis. This perspective offers the author’s reflections on effective learning and teaching strategies for this purpose, after running such a course for the past 10 years at Griffith University. In earlier years, students’ have complained about lack of direction and overloading, which are common issues being reported in PBL courses. In response, we have implemented scaffolding and balanced evaluation criteria for assessment, providing formative feedback, and we have designed integrated assessment items. As a result, average marks for the cohort and the percentage of students that receive the grade of high distinction have increased in the past five years. These strategies might be of help at other learning institutions that offer similar courses.

scholarly journals DESIGN OF 0.9-2.1 GHZ LOW-NOISE AMPLIFIER ON PRINTED CIRCUIT BOARD USING “VISUAL” DESIGN TOOLS

2014 ◽  
Vol 17 (09) ◽  
pp. 145-152
Author(s):  
Alexander Andreevich Samuilov ◽  
◽  
Igor Miroslavovich Dobush ◽  
Aleksey Anatolevich Kalentev ◽  
◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Circuit Board ◽  
Visual Design ◽  
Design Tools ◽  
Printed Circuit ◽  
Noise Amplifier

Meander Delay Compensation in High-Speed Digital Multilayer Packages

2012 ◽  
Vol 2012 (1) ◽  
pp. 000334-000339 ◽  
Author(s):  
Robert Frye ◽  
Kai Liu
Keyword(s):  
High Speed ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Propagation Time ◽  
Design Tools ◽  
Delay Compensation ◽  
Printed Circuit ◽  
Bga Packages ◽  
Timing Skew

The routing of multi-trace digital signal buses in printed circuit boards often results in mismatches in the lengths of the lines. This results in mismatched propagation time, referred to as “timing skew” in a digital system. A common method that is used to compensate for this is to add meander sections of line to lengthen the signal path length. Many advanced circuit board design tools have the capability to perform this compensation automatically. Advanced Ball Grid Array (BGA) packages are fabricated using fine-line multilayer laminate substrates or they are built up using multilayer wafer-scale processes. The design tools for these types of packages have evolved from printed circuit board tools and typically use the same methods and principles. It is very common in BGA packages for high-speed digital applications to use meander trace patterns to match the trace lengths of high speed bus interconnections either from the chip to the solder balls or between chips in a multi-chip package. However, electromagnetic simulation of these packages shows that despite the use of these techniques to match the physical length of the traces, electrical lengths often vary by as much as a factor of two. Examples of such packages are presented and analyzed. The resulting timing skew is not a significant problem in most current applications, since the overall delay is small compared with the clock interval. But with emerging applications pushing well beyond 10Gb/s, timing skew in packages will be an important consideration. The reasons for the ineffectiveness of meander delay compensation are discussed, and are demonstrated by some simple simulations.

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application

2012 ◽  
Vol 2012 (1) ◽  
pp. 001038-001045 ◽  
Author(s):  
Sheng-Tsai Wu ◽  
John H. Lau ◽  
Heng-Chieh Chien ◽  
Yu-Lin Chao ◽  
Ra-Min Tain ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Creep Strain ◽  
High Power ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Random Access ◽  
Circuit Board ◽  
3D Ic ◽  
Silicon Vias

In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.

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