Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

scholarly journals Digital logic gates in soft, conductive mechanical metamaterials

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Charles El Helou ◽  
Philip R. Buskohl ◽  
Christopher E. Tabor ◽  
Ryan L. Harne
Keyword(s):  
Integrated Circuits ◽  
Electronic Materials ◽  
Polymer Networks ◽  
Conductive Polymer ◽  
Network Connectivity ◽  
Logic Gates ◽  
Boolean Logic ◽  
Digital Logic ◽  
Mechanical Metamaterials ◽  
Logic Operations

AbstractIntegrated circuits utilize networked logic gates to compute Boolean logic operations that are the foundation of modern computation and electronics. With the emergence of flexible electronic materials and devices, an opportunity exists to formulate digital logic from compliant, conductive materials. Here, we introduce a general method of leveraging cellular, mechanical metamaterials composed of conductive polymers to realize all digital logic gates and gate assemblies. We establish a method for applying conductive polymer networks to metamaterial constituents and correlate mechanical buckling modes with network connectivity. With this foundation, each of the conventional logic gates is realized in an equivalent mechanical metamaterial, leading to soft, conductive matter that thinks about applied mechanical stress. These findings may advance the growing fields of soft robotics and smart mechanical matter, and may be leveraged across length scales and physics.

Novel vs Conventional Bipolar Logic Circuit Topologies in 4H-SiC

2016 ◽  
Vol 858 ◽  
pp. 1103-1106 ◽  
Author(s):  
Hazem Elgabra ◽  
Amna Siddiqui ◽  
Shakti Singh
Keyword(s):  
Silicon Carbide ◽  
Electrical Properties ◽  
Integrated Circuits ◽  
Logic Circuit ◽  
Digital Logic ◽  
Harsh Environment ◽  
The Novel ◽  
Attractive Candidate ◽  
Silicon Based

Silicon Carbide (SiC) is an attractive candidate for integrated circuits (ICs) in harsh environment applications due to its superior inherent electrical properties. Though current research is geared towards adapting existing silicon based digital logic technologies to 4H-SiC, the true merit of each technology in 4H-SiC has remained unclear. Creating logic technologies specifically for 4H-SiC, taking into account its electrical properties, is an area which remains unexplored. In this paper, we present a novel bipolar logic technology that is designed and optimized for 4H-SiC, and compare its performance with the prevalent bipolar technologies. The results show that the novel logic technology not only compares well with the conventional technologies in performance, but also features simpler design, smaller footprint, and a low transistor count.

scholarly journals Bitstream Photon Counting Chirped AM Lidar with a Digital Logic Local Oscillator

2019 ◽  
Author(s):  
Brian Redman
Keyword(s):  
Integrated Circuits ◽  
Signal To Noise Ratio ◽  
Logic Gate ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Digital Logic ◽  
Oxide Semiconductor ◽  
Photon Counting Detector ◽  
Analog Electronics

This paper introduces a new concept for the local oscillator (LO) for the Photon Counting Chirped Amplitude Modulation Lidar (PC-CAML). Rather than using a radio-frequency (RF) analog LO applied electronically either in post-detection mixing or via opto-electronic mixing (OEM) at the detector, or applied via pre-detection mixing using an optical intensity modulator as in previous systems, the new method mixes the single-bit binary counts from the photon counting detector with a single-bit binary LO using an AND binary digital logic gate. This type of LO is called the Digital Logic Local Oscillator (DLLO), and the resulting PC-CAML system is a type of bitstream lidar called bitstream PC-CAML (patent pending).The key advantage of the DLLO in the bitstream PC-CAML is that it replaces bulky, power-hungry, and expensive wideband RF analog electronics with single-bit digital logic components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous PCCAML systems.This paper introduces the DLLO for bitstream PC-CAML concept, presents the initial signal-to-noise-ratio (SNR) theory with comparisons to Monte Carlo simulation results, and makes suggestions for future work on this concept.

scholarly journals Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1936
Author(s):  
Karel Appels ◽  
Jeffrey Prinzie
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Cmos Technology ◽  
Digital Logic ◽  
Radiation Environment ◽  
Digital Integrated Circuits ◽  
Distributed Approach ◽  
Implementation Methodology ◽  
Logic Cells ◽  
Radiation Tolerant

This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

scholarly journals Complementing Digital Logic Design with Logisim

2013 ◽  
Vol 11 (1) ◽  
pp. 69
Author(s):  
SA Al-Busaidi
Keyword(s):  
Integrated Circuits ◽  
Open Source ◽  
Open Source Software ◽  
Digital Logic ◽  
Logic Design ◽  
Theoretical Concepts ◽  
Complete Set

Classified as free and open source software (FOSS), Logisim is a delightful tool that can easily be used to reinforce a solid understanding of the theoretical concepts related to a digital logic design course. Unlike LogicWorks, one of the most attractive features of Logisim is its ability to include user built libraries. This can result in the development of a library that models the complete set of integrated circuits (ICs) required for a digital logic design course. As a consequence, numerous merits can be observed regarding a student's learning level within such a course. 

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

The study of interfacial reactions of nickel thin films on GaAs

1983 ◽  
Vol 41 ◽  
pp. 156-157
Author(s):  
L.J. Chen ◽  
Y.F. Hsieh
Keyword(s):  
Thin Films ◽  
Integrated Circuits ◽  
Interfacial Reactions ◽  
Metal Contacts ◽  
Nickel Thin Films ◽  
Thin Foils ◽  
The Status ◽  
Si Doped ◽  
Electron Microscopes

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Failure Analysis With the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 482-483
Author(s):  
John R. Devaney
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
High Reliability ◽  
Military Applications ◽  
Small Structure ◽  
Useful Life ◽  
Insight Into ◽  
Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

Sign in / Sign up

Export Citation Format

Share Document