A crest factor-based technique for the analysis of polluted insulator leakage current under harmonically distorted supply voltage

2021 ◽  
Author(s):  
Apu Banik ◽  
Shawn Nielsen ◽  
Ghavameddin Nourbakhsh
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Crest Factor

20 kV 4H-SiC N-IGBTs

2014 ◽  
Vol 778-780 ◽  
pp. 1030-1033 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
Michael J. O'Loughlin ◽  
Jack Clayton ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Leakage Current ◽  
Supply Voltage ◽  
Boost Converter ◽  
Power Switching ◽  
Switching Device ◽  
Blocking Voltage ◽  
Off Time ◽  
Drift Layer ◽  
Stop Buffer

A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a VF of 6.4 V at an IC of 20 A, and a differential Ron,sp of 28 mΩ-cm2. Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.

Highly Reliable Metal Gate nMOSFETs by Improved CVD-WSix films with Work Function of 4.3eV

2004 ◽  
Vol 811 ◽  
Author(s):  
Kazuaki Nakajima ◽  
Hiroshi Nakazawa ◽  
Katsuyuki Sekine ◽  
Kouji Matsuo ◽  
Tomohiro Saito ◽  
...  
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Power Supply ◽  
Supply Voltage ◽  
Gate Length ◽  
Gate Electrode ◽  
Metal Gate ◽  
Power Supply Voltage ◽  
Drive Current

ABSTRACTIn this paper, we first propose an improved CVD-WSix metal gate suitable for use with nMOSFETs. Work function of CVD-WSi3.9 gate estimated from C-V measurements was 4.3eV. The nMOSFET using CVD-WSi3.9 gate electrode showed that Vth variation of L/W=1 μm/10μm nMOSFETs can be suppressed to be lower than 8mV in 22chip. In CVD-WSi3.9 gate MOSFETs with gate length of 50nm, a drive current of 636μA/μm was achieved for off-state leakage current of 35nA/μm at 1.0V of power supply voltage. By using CVD-WSi3.9 gate electrode, highly reliable metal gate nMOSFETs can be realized.

scholarly journals Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

2019 ◽  
Vol 7 (3) ◽  
pp. 11-18
Author(s):  
Yogesh Kulshethra ◽  
Manish Kule
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Leakage Power ◽  
Power Gating ◽  
Design Constraint ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Look Ahead ◽  
Simulation Results ◽  
Gating Scheme

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS

2015 ◽  
Vol 4 (3) ◽  
pp. 178
Author(s):  
Ajeesh Kumar ◽  
N. Saraswathi
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Circuits ◽  
Flip Flop ◽  
Sleep Transistors ◽  
Power Delay Product ◽  
Charge Mode ◽  
Logic Level

This paper introduces a Low Power Dual DynamicNode FlipFlop(DDFF) using Sleep Transistor with NMOS. Theproposed design retains the logic level till the end of evaluation and pre-charge mode. The low power DDFF architecturethat combines the advantages of dynamic and static CMOSstructures. The Sleep Transistors approach are used for leakagepower reduction. It reduces leakage current in ideal mode.The performance of the proposed flip flop was compared withthe conventional dual dynamic node flip flop (DDFF) in 90nmCMOS technology with 1.2v supply voltage at room temperatures.Also, conventional DDFF and DDFF using Sleep Transistor withNMOS are compared with other complicated designs and realizesby a 4-bit Johnson up and down counter. The performanceimprovements indicates that the proposed designs are suited formodern high-performance CMOS circuits where leakage powerand power delay product overhead are of major concern

scholarly journals COMBINATION OF SYNTHETIC HIGH-PERFORMANCE RF AMPLIFICATION TECHNIQUES

T-Comm ◽  
2021 ◽  
Vol 15 (9) ◽  
pp. 11-16
Author(s):  
Oleg V. Varlamov ◽  
◽  
Dang C. Nguyen ◽  
Sergey E. Grychkin ◽  
◽  
...  
Keyword(s):  
High Performance ◽  
High Efficiency ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Rf Power Amplifiers ◽  
Rf Power ◽  
Crest Factor ◽  
Combined Use ◽  
Radio Signals ◽  
Element Base

To amplify modern high crest factor telecommunication radio signals with high efficiency, switching operation modes of transistors and synthetic amplification methods are used. The most common of these are the Kahn method (EER – envelope elimination and restoration) and the outphasing method. However, application of these methods has a number of technological (in terms of element base capabilities) limitations on the bandwidth and dynamic range of amplified signal. To expand high-efficiency RF power amplifiers field of application, the possibilities of combination several different synthetic amplification techniques are being considered. Expressions are obtained for the theoretically achievable efficiency when combining the outphasing method with a bridge power combiner and pulse-step modulation of supply voltage. The dependence of average efficiency on the number of supply voltage levels is determined. RF amplified signal bandwidth and its dynamic range determine the minimum required pulse width of the PWM modulator for the EER amplifier. Variants of these characteristics dependence on the number of supply voltage levels are discussed with combined use of PWM and pulse-step modulation of the supply voltage. Directions for further research are formulated.

Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

2012 ◽  
Vol 548 ◽  
pp. 885-889 ◽  
Author(s):  
Manisha Pattanaik ◽  
Balwinder Raj ◽  
Shashikant Sharma ◽  
Anjan Kumar
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Full Adder ◽  
Mode Analysis ◽  
Mode Transition ◽  
Additional Mode ◽  
Ground Bounce

In this paper a high performance diode based trimode Multi-Threshold CMOS (MTCMOS) technique is introduced which minimizes standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. hold mode. Analysis of trimode MTCMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to evaluate the effectiveness of diode based trimode Multi-Threshold CMOS technique, simulation has been done on low power 16-bit full adder circuit with BPTM 90nm technology at room temperature with supply voltage of 1 V. Diode based trimode Multi-Threshold CMOS technique reduces ground bounce noise by 89.36% and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

2021 ◽  
pp. 359-370
Author(s):  
Amol S. Sankpala, D. J. Peteb
Keyword(s):  
Leakage Current ◽  
Retention Time ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Average Power ◽  
Random Access ◽  
Cmos Technology ◽  
Double Gate ◽  
Silicon Area ◽  
Nanometer Regime

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.

LEAKAGE CURRENT REDUCTION IN VLSI SYSTEMS

2002 ◽  
Vol 11 (06) ◽  
pp. 621-635 ◽  
Author(s):  
DAVID BLAAUW ◽  
STEVE MARTIN ◽  
TREVOR MUDGE ◽  
KRISZTIAN FLAUTNER
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Analytical Models ◽  
Dominant Factor ◽  
Total Power ◽  
Sleep Mode ◽  
Clock Frequency ◽  
Total Power Consumption ◽  
Body Bias

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

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