scholarly journals Fully Integrated Memristor and Its Application on the Scroll-Controllable Hyperchaotic System

Complexity ◽  
2019 ◽  
Vol 2019 ◽  
pp. 1-8 ◽  
Author(s):  
Jie Jin ◽  
Li Cui
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Nonlinear Function ◽  
Cmos Process ◽  
Hyperchaotic System ◽  
Single Chip ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Memristor Emulator

In this paper, a fully integrated memristor emulator using operational amplifiers (OAs) and analog multipliers is simulated. Based on the fully integrated memristor, a scroll-controllable hyperchaotic system is presented. By controlling the nonlinear function with programmable switches, the memristor-based hyperchaotic system achieves controllable scroll numbers. Moreover, the memristor-based hyperchaotic system is fully integrated in one single chip, and it achieves lower supply voltage, lower power dissipation, and smaller chip area. The fully integrated memristor and memristor-based hyperchaotic system are verified with the GlobalFoundries’ 0.18 μm CMOS process using Cadence IC Design Tools. The postlayout simulation results demonstrate that the memristor-based fully integrated hyperchaotic system consumes 90.5 mW from ±2.5 V supply voltage and it takes a compact chip area of 1.8 mm2.

Low Voltage Low Power Fully Integrated Chaos Generator

2018 ◽  
Vol 27 (10) ◽  
pp. 1850155 ◽  
Author(s):  
Jie Jin ◽  
LV Zhao
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic Components ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Chaos Generator ◽  
Wide Range

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback Structure

2019 ◽  
Vol 28 (08) ◽  
pp. 1950125
Author(s):  
Jianqun Ding ◽  
Lijun Huang ◽  
Xianwu Mi ◽  
Dajiang He ◽  
Shenghai Chen ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Low Power Dissipation ◽  
Feedback Structure ◽  
Voltage Swing ◽  
Low Supply Voltage ◽  
Capacitive Feedback

In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325 GHz and 2.435 GHz, and the phase noise is [Formula: see text]128.2 dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535 mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198 dBc/Hz.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
Active Inductors ◽  
Low Pass ◽  
Optical Applications ◽  
Fifth Order

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

scholarly journals A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 860
Author(s):  
Shao-Ku Kao
Keyword(s):  
Duty Cycle ◽  
Delay Line ◽  
Supply Voltage ◽  
Cmos Process ◽  
Delay Lines ◽  
Clock Frequency ◽  
Quantization Method ◽  
Total Delay ◽  
Chip Area ◽  
Measurement Results

This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

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