ULTRARAM™: a low-energy, high-endurance, compound-semiconductor memory on silicon

Abstract ULTRARAM is a non-volatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here we report its implementation on a Si substrate; a vital step towards cost-effective mass production. Sample growth using molecular beam epitaxy commenced with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III-V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10-ms duration program/erase pulses of ~2.5 V, a remarkably fast switching speed for 10- and 20-µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices revealed retention in excess of 1000 years, and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

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ULTRARAM™: a low-energy, high-endurance, compound-semiconductor memory on silicon

10.21203/rs.3.rs-690726/v1 ◽

2021 ◽

Author(s):

Peter Hodgson ◽

Dominic Lane ◽

Peter Carrington ◽

Evangelia Delli ◽

Richard Beanland ◽

...

Keyword(s):

Low Voltage ◽

Random Access ◽

Cost Effective ◽

Low Energy ◽

Switching Speed ◽

Nucleation Layer ◽

Semiconductor Memory ◽

Resonant Tunnelling ◽

Non Volatile Memory ◽

Small Device

Abstract ULTRARAM™ is a non-volatile memory with the potential to achieve fast, ultra-low-energy electron storage in a floating gate accessed through a triple-barrier resonant tunnelling heterostructure. Here we report the implementation of ULTRARAM™ on a Si substrate; a vital step towards cost-effective mass production. Sample growth was carried out using molecular beam epitaxy, by first depositing an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III-V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10-ms duration program/erase pulses of ~2.5 V, a remarkably fast switching speed for 10- and 20-µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of the devices revealed retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, exceeding very recent results for similar devices on GaAs substrates.

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2D Materials Based Optoelectronic Memory: Convergence of Electronic Memory and Optical Sensor

Research ◽

10.34133/2019/9490413 ◽

2019 ◽

Vol 2019 ◽

pp. 1-17 ◽

Cited By ~ 15

Author(s):

Feichi Zhou ◽

Jiewei Chen ◽

Xiaoming Tao ◽

Xinran Wang ◽

Yang Chai

Keyword(s):

Data Storage ◽

Optical Sensors ◽

2D Materials ◽

Random Access ◽

Image Data ◽

Electronic System ◽

Electronic Systems ◽

Switching Speed ◽

Sensory Data ◽

Fast Switching

The continuous development of electron devices towards the trend of “More than Moore” requires functional diversification that can collect data (sensors) and store (memories) and process (computing units) information. Considering the large occupation proportion of image data in both data center and edge devices, a device integration with optical sensing and data storage and processing is highly demanded for future energy-efficient and miniaturized electronic system. Two-dimensional (2D) materials and their heterostructures have exhibited broadband photoresponse and high photoresponsivity in the configuration of optical sensors and showed fast switching speed, multi-bit data storage, and large ON/OFF ratio in memory devices. In addition, its ultrathin body thickness and transfer process at low temperature allow 2D materials to be heterogeneously integrated with other existing materials system. In this paper, we overview the state-of-the-art optoelectronic random-access memories (ORAMs) based on 2D materials, as well as ORAM synaptic devices and their applications in neural network and image processing. The ORAM devices potentially enable direct storage/processing of sensory data from external environment. We also provide perspectives on possible directions of other neuromorphic sensor design (e.g., auditory and olfactory) based on 2D materials towards the future smart electronic systems for artificial intelligence.

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Resistance Non-volatile Memory – RRAM

MRS Proceedings ◽

10.1557/proc-0997-i05-03 ◽

2007 ◽

Vol 997 ◽

Author(s):

Alex Ignatiev ◽

Naijuan Wu ◽

Xin Chen ◽

Yibo Nian ◽

Christina Papagianni ◽

...

Keyword(s):

Low Voltage ◽

Electric Pulse ◽

Random Access ◽

Analytical Techniques ◽

Resistance Change ◽

Device Development ◽

Thin Oxide Film ◽

Resistance Random Access Memory ◽

Change Effect ◽

Non Volatile Memory

AbstractElectric-pulse induced resistance (EPIR) change effect encompasses the reversible change of resistance of a thin oxide film under the application of short, low voltage pulses. The phenomenon is widely observed in complex and binary oxides, and is the basis for development of non-volatile resistance random access memory (RRAM). A variety of analytical techniques have been employed to understand the origin of the resistance change with recent data yielding a model incorporating oxygen ion/vacancy diffusion and pile-up near the interface region of the oxide at the impervious metal interface. Further efforts are still required to fine tune the model and apply it to the optimization of RRAM device development.

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Memristive devices based on mass printed organic resistive switching layers

Applied Physics A ◽

10.1007/s00339-021-04851-9 ◽

2021 ◽

Vol 127 (9) ◽

Author(s):

Jörg Strutwolf ◽

Yong Chen ◽

Johann Ullrich ◽

Martin Dehnert ◽

Arved C. Hübler

Keyword(s):

Random Access ◽

Electrical Characterization ◽

Cost Effective ◽

Resistive Random Access Memory ◽

Poly Vinyl Alcohol ◽

Resistive Memory ◽

Resistive Layer ◽

Roll To Roll ◽

Non Volatile Memory ◽

Microscopic Studies

AbstractResistive random-access memory is a candidate for next-generation non-volatile memory architectures. In this study, we use flexographic roll-to-roll printing technology for deposition of the resistive layer, a printing method that allows fast and cost-effective fabrication to create non-volatile resistive memory devices. Metal-free organic polymers blends composed of poly(methyl methacrylate) (PMMA) and a surplus of poly(vinyl alcohol) (PVA) serve as the active layer. Microscopic studies of the roll-to-roll printed layers show circular domains of PMMA embedded in PVA. The influence of the PMMA content in the polymer blend is investigated with respect to the performance and reliability of the resistive memory cells. Electrical characterization reveals a retention time of at least eleven days, a Roff/Ron ratio of approx. two orders and write/erase voltages of + 1/−2 V.

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High-Density Memristor-CMOS Ternary Logic Family

10.36227/techrxiv.12598559 ◽

2020 ◽

Author(s):

Xiaoyuan Wang ◽

Pengfei Zhou ◽

Jason Eshraghian ◽

Chih-Yang Lin ◽

Herbert Ho-Ching Iu ◽

...

Keyword(s):

Indium Tin Oxide ◽

Practical Implementation ◽

Switching Speed ◽

High Data ◽

Fast Switching ◽

Data Density ◽

Order Of Magnitude ◽

High Transconductance ◽

Logic Functions ◽

Magnitude Improvement

<div>This paper presents the first experimental demonstration</div><div>of a ternary memristor-CMOS logic family. We systematically</div><div>design, simulate and experimentally verify the primitive</div><div>logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.</div>

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Analysis of 6T SRAM Cell in Different Technologies

Circulation in Computer Science ◽

10.22632/ccs-2017-mcsp026 ◽

2017 ◽

Vol MCSP2017 (01) ◽

pp. 7-10 ◽

Cited By ~ 2

Author(s):

Subhashree Rath ◽

Siba Kumar Panda

Keyword(s):

Low Power ◽

Data Storage ◽

Low Voltage ◽

Random Access ◽

Storage Device ◽

Cmos Process ◽

Process Technology ◽

Digital Devices ◽

Noise Margin ◽

Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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Implications of NVM Based Storage on Memory Subsystem Management

Applied Sciences ◽

10.3390/app10030999 ◽

2020 ◽

Vol 10 (3) ◽

pp. 999

Author(s):

Hyokyung Bahn ◽

Kyungwoon Cho

Keyword(s):

Random Access ◽

Disk Drive ◽

Main Memory ◽

Memory Storage ◽

Storage Device ◽

Storage Devices ◽

Large Memory ◽

Memory Subsystems ◽

Non Volatile Memory ◽

Management Techniques

Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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All-Organic, Low Voltage, Transparent and Compliant Organic Field-Effect Transistor Fabricated by Means of Large-Area, Cost-Effective Techniques

Applied Sciences ◽

10.3390/app10196656 ◽

2020 ◽

Vol 10 (19) ◽

pp. 6656

Author(s):

Stefano Lai ◽

Giulia Casula ◽

Pier Carlo Ricci ◽

Piero Cosseddu ◽

Annalisa Bonfiglio

Keyword(s):

Field Effect ◽

Low Voltage ◽

Field Effect Transistors ◽

High Mobility ◽

Chemical Vapor ◽

Cost Effective ◽

Large Area ◽

Parylene C ◽

Biomedical Sensing ◽

Novel Applications

The development of electronic devices with enhanced properties of transparency and conformability is of high interest for the development of novel applications in the field of bioelectronics and biomedical sensing. Here, a fabrication process for all organic Organic Field-Effect Transistors (OFETs) by means of large-area, cost-effective techniques such as inkjet printing and chemical vapor deposition is reported. The fabricated device can operate at low voltages (as high as 4 V) with ideal electronic characteristics, including low threshold voltage, relatively high mobility and low subthreshold voltages. The employment of organic materials such as Parylene C, PEDOT:PSS and 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS pentacene) helps to obtain highly transparent transistors, with a relative transmittance exceeding 80%. Interestingly enough, the proposed process can be reliably employed for OFET fabrication over different kind of substrates, ranging from transparent, flexible but relatively thick polyethylene terephthalate (PET) substrates to transparent, 700-nm-thick, compliant Parylene C films. OFETs fabricated on such sub-micrometrical substrates maintain their functionality after being transferred onto complex surfaces, such as human skin and wearable items. To this aim, the electrical and electromechanical stability of proposed devices will be discussed.

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