Verification of Open Core Protocol using System Verilog and UVM
2021 ◽
Vol 9
(VI)
◽
pp. 5501-5510
Keyword(s):
The ever-increasing complexity of the integrated circuits design and the scale of the projects are making verification more challenging and time-consuming. As a result, the rapidly expanding VLSI industry necessitates a highly reliable and robust verification mechanism. In this paper, System Verilog Verification and Universal Verification Methodologies were adopted to verify the Accellera Open Core Protocol 3.0 as per specifications. According to the verification plan, the environment was developed under a dynamic approach, and the passive aspects included scoreboard, functional coverage, and system verilog assertions. The presented frameworks had verified OCP achieving successful dataflow signals extensions as per results.
2019 ◽
Vol 8
(6)
◽
pp. 5254-5260
Keyword(s):
1983 ◽
Vol 41
◽
pp. 160-161
1983 ◽
Vol 41
◽
pp. 86-89
Keyword(s):
1972 ◽
Vol 30
◽
pp. 482-483
1991 ◽
Vol 49
◽
pp. 898-899
Keyword(s):
1976 ◽
Vol 34
◽
pp. 456-457
1992 ◽
Vol 50
(2)
◽
pp. 1684-1685
1986 ◽
Vol 44
◽
pp. 736-737
Keyword(s):
1986 ◽
Vol 44
◽
pp. 652-653