scholarly journals Design and Analysis of Gate All Around Tunnel FET based SRAM

2019 ◽  
Vol 8 (9) ◽  
pp. 1492-1500
Keyword(s):  
Circuit Simulation ◽  
Research Work ◽  
Device Simulation ◽  
Leakage Power ◽  
Subthreshold Slope ◽  
Noise Margin ◽  
Tunnel Fet ◽  
Sram Cell ◽  
Simulation Results ◽  
Strong Control

Tunnel FETs (TFETs) possess all required characteristics for replacing MOSFET device in circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular Gate-All-Around (GAA) TFET device configuration exhibits higher ION/IOFF ratio and strong control of the gate terminal over the channel. The main objective of this research work is to explore the prospects of using GAATFET device topology for designing low power and reliable SRAM cell. In this work both n-type and p-type Tunnel FET devices have been designed and simulated using Cogenda Visual TCAD tool. Verilog-A model relying on look up tables that are extracted through device simulations has been designed for performing circuit simulations of 6T and 8T SRAM cell involving these novel devices. Device simulation results show that both NTFET and PTFET devices exhibits excellent ION/IOFF ratio and steep subthreshold slope. NTFET device simulation results show 21.2 mV/decade of subthreshold slope and ION/IOFF ratio of 1013. PTFET device has ON current of the similar order as that of NTFET and has extremely low value of OFF current of less than 1 pA. Circuit simulation results show that by using optimized sizing of transistors in outward NTFET access transistor based 6T SRAM cell leads to reliable and fast read and write operation with acceptable values of noise margin. 6T TFET based SRAM cell achieves leakage power reduction by 77.5% in comparison to leakage power consumed by 8T TFET based SRAM thereby making it a favorable choice for memory design.

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

2019 ◽  
Vol 29 (05) ◽  
pp. 2050067
Author(s):  
S. R. Mansore ◽  
R. S. Gamad ◽  
D. K. Mishra
Keyword(s):  
High Performance ◽  
Model Simulation ◽  
Random Access ◽  
Leakage Power ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Operation Characteristics ◽  
Static Noise

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

Variability aware FinFET SRAM cell with improved stability and power for low power applications

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 196-207
Author(s):  
Shilpi Birla
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Leakage Power ◽  
Static Noise Margin ◽  
Content Type ◽  
Noise Margin ◽  
Sram Cell ◽  
Memory Circuits ◽  
The Stability ◽  
Static Noise

Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits. Design/methodology/approach In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. Findings The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384  mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed. Research limitations/implications The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used. Practical implications SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array. Social implications The cell can be used for SRAM memory for low power consumptions. Originality/value The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

scholarly journals Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

2021 ◽  
Vol 11 (24) ◽  
pp. 12151
Author(s):  
Tae Jun Ahn ◽  
Sung Kyu Lim ◽  
Yun Seop Yu
Keyword(s):  
Circuit Simulation ◽  
Three Dimensional ◽  
Propagation Delay ◽  
Model Parameters ◽  
Interface Trap ◽  
Flip Flop ◽  
Trap Charge ◽  
Noise Margin ◽  
Simulation Results ◽  
Trap Charges

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

scholarly journals 9T SRAM CELL WITH MT-SVL TECHNIQUE FOR LEAKAGE POWER REDUCTION

2021 ◽  
Vol 9 (2) ◽  
pp. 1139-1143
Author(s):  
Kothamasu Jyothi, Et. al.
Keyword(s):  
Power Dissipation ◽  
Power Reduction ◽  
Leakage Power ◽  
Voltage Level ◽  
Technology Scaling ◽  
Sram Cell ◽  
Simulation Results ◽  
Leakage Power Dissipation

With the technology scaling there is a decrease in transistor size and increase in number of the transistors per a chip. It causes tremendous increase in complexity and the power dissipation of circuits. This paper mainly focuses on reduction of leakage power dissipation in SRAM 9T cells by employing multi threshold self controllable voltage level circuits  (LSVL & USVL). The Simulation results show that with the employment of MT-SVL technique, leakage power is being reduced compared to the improved SVL technique. The overall simulation is done with CMOS 180nm technology, using the tool of Cadence Virtuoso.

QoS aware Multi-Path Routing using Link Scheduling Algorithm

2019 ◽  
Vol 09 ◽  
Author(s):  
Satyasrikanth Palle ◽  
Shivashankar
Keyword(s):  
Cellular Networks ◽  
Scheduling Algorithm ◽  
Research Work ◽  
Scheduling Algorithms ◽  
Turnaround Time ◽  
Link Scheduling ◽  
Spatial Reuse ◽  
Mobile Cellular ◽  
Simulation Results ◽  
End To End

Objective: The demand for Cellular based multimedia services is growing day by day, in order to fulfill such demand the present day cellular networks needs to be upgraded to support excessive capacity calls along with high data accessibility. Analysis of traffic and huge network size could become very challenging issue for the network operators for scheduling the available bandwidth between different users. In the proposed work a novel QoS Aware Multi Path scheduling algorithm for smooth CAC in wireless mobile networks. The performance of the proposed algorithm is assessed and compared with existing scheduling algorithms. The simulation results show that the proposed algorithm outperforms existing CAC algorithms in terms of throughput and delay. The CAC algorithm with scheduling increases end-to-end throughput and decreases end-to-end delay. Methods: The key idea to implement the proposed research work is to adopt spatial reuse concept of wireless sensor networks to mobile cellular networks. Spatial reusability enhances channel reuse when the node pairs are far away and distant. When Src and node b are communicating with each other, the other nodes in the discovered path should be idle without utilizing the channel. Instead the other nodes are able to communicate parallelly the end-to-end throughput can be improved with acceptable delay. Incorporating link scheduling algorithms to this key concept further enhances the end-to-end throughput with in the turnaround time. So, in this research work we have applied spatial reuse concept along with link scheduling algorithm to enhance end-to-end throughput with in turnaround time. The proposed algorithm not only ensures that a connection gets the required bandwidth at each mobile node on its way by scheduling required slots to meet the QoS requirements. By considering the bandwidth requirement of the mobile connections, the CAC module at the BS not only considers the bandwidth requirement but also conforming the constrains of system dealy and jitter are met. Result: To verify the feasibility and effectiveness of our proposed work, with respect to scheduling the simulation results clearly shows the throughput improvement with Call Admission Control. The number of dropped calls is significantly less and successful calls are more with CAC. The percentage of dropped calls is reduced by 9 % and successful calls are improved by 91%. The simulation is also conducted on time constraint and ratio of dropped calls are shown. The total time taken to forward the packets and the ration of dropped calls is less when compared to non CAC. On a whole the CAC with scheduling algorithms out performs existing scheduling algorithms. Conclusion: In this research work we have proposed a novel QoS aware scheduling algorithm that provides QoS in Wireless Cellular Networks using Call Admission Control (CAC). The simulation results show that the end-to-end throughput has been increased by 91% when CAC is used. The proposed algorithm is also compared with existing link scheduling algorithms. The results reveal that CAC with scheduling algorithm can be used in Mobile Cellular Networks in order to reduce packet drop ratio. The algorithm is also used to send the packets within acceptable delay.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

A Dicode Signaling Scheme for Capacitively Coupled Interface

2011 ◽  
Vol 497 ◽  
pp. 296-305
Author(s):  
Yasushi Yuminaka ◽  
Kyohei Kawano
Keyword(s):  
Partial Response ◽  
Data Transmission ◽  
High Speed ◽  
Circuit Simulation ◽  
Frequency Bandwidth ◽  
Capacitively Coupled ◽  
Limited Frequency ◽  
Simulation Results ◽  
Response Coding ◽  
The Impact

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

2012 ◽  
Vol 542-543 ◽  
pp. 769-774
Author(s):  
Qun Ling Yu ◽  
Na Bai ◽  
Yan Zhou ◽  
Rui Xing Li ◽  
Jun Ning Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Optimal Operation ◽  
Reduction Technique ◽  
Total Speed ◽  
Sense Amplifier ◽  
Simulation Results ◽  
A New Technique ◽  
Total Energy Dissipation

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

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