scholarly journals Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Nanomaterials ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 646
Author(s):  
Qingzhu Zhang ◽  
Jie Gu ◽  
Renren Xu ◽  
Lei Cao ◽  
Junjie Li ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Ground Plane ◽  
Electrical Characteristics ◽  
Release Process ◽  
Device Structures ◽  
Bulk Substrate ◽  
P Type ◽  
Aided Design ◽  
20 Nm ◽  
Wet Etch

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

scholarly journals Ground Plane Impact on Performance of Relaxed Ge FinFETs

2019 ◽  
Vol 14 (1) ◽  
pp. 1-6
Author(s):  
Alberto Vinícius Oliveira ◽  
Guilherme Vieira Gonçalves ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
Jérôme Mitard ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Doping Concentration ◽  
Ground Plane ◽  
Subthreshold Swing ◽  
Voltage Variation ◽  
Electrostatic Coupling ◽  
P Type ◽  
Aided Design ◽  
Channel Region

The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.

scholarly journals Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1422
Author(s):  
Ki-Yeong Kim ◽  
Joo-Seok Noh ◽  
Tae-Young Yoon ◽  
Jang-Hyun Kim
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Buffer Layers ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Insulated Gate Bipolar Transistor ◽  
Computer Aided ◽  
Long Time ◽  
Tcad Simulation ◽  
Aided Design

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.

scholarly journals A Breakdown Enhanced AlGaN/GaN Schottky Barrier Diode with the T-Anode Position Deep into the Bottom Buffer Layer

Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 91 ◽  
Author(s):  
Youlei Sun ◽  
Ying Wang ◽  
Jianxiang Tang ◽  
Wenju Wang ◽  
Yifei Huang ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Buffer Layer ◽  
Computer Aided Design ◽  
Tunneling Current ◽  
Cathode Region ◽  
Schottky Barrier Diode ◽  
Electrical Characteristics ◽  
Edge Termination ◽  
Dimensional Electron Gas ◽  
Aided Design

In this paper, an AlGaN/GaN Schottky barrier diode (SBD) with the T-anode located deep into the bottom buffer layer in combination with field plates (TAI-BBF FPs SBD) is proposed. The electrical characteristics of the proposed structure and the conventional AlGaN/GaN SBD with gated edge termination (GET SBD) were simulated and compared using a Technology Computer Aided Design (TCAD) tool. The results proved that the breakdown voltage (VBK) in the proposed structure was tremendously improved when compared to the GET SBD. This enhancement is attributed to the suppression of the anode tunneling current by the T-anode and the redistribution of the electric field in the anode–cathode region induced by the field plates (FPs). Moreover, the T-anode had a negligible effect on the two-dimensional electron gas (2DEG) in the channel layer, so there is no deterioration in the forward characteristics. After being optimized, the proposed structure exhibited a low turn-on voltage (VT) of 0.53 V and a specific on-resistance (RON,sp) of 0.32 mΩ·cm2, which was similar to the GET SBD. Meanwhile, the TAI-BBF FP SBD with an anode-cathode spacing of 5 μm achieved a VBK of 1252 V, which was enhanced almost six times compared to the GET SBD with a VBK of 213 V.

scholarly journals A Proposed Method for Improving the Performance of P-Type GaAs IMPATTs

1970 ◽  
Vol 1 (1) ◽  
Author(s):  
H. A. El-Motaafy
Keyword(s):  
Computer Aided Design ◽  
Phase Relationship ◽  
Extensive Study ◽  
Microwave Engineering ◽  
Sinusoidal Waveform ◽  
Computer Simulation Program ◽  
Terminal Voltage ◽  
Physical Effects ◽  
P Type ◽  
Aided Design

A special waveform is proposed and assumed to be the optimum waveform for p-type GaAs IMPATTs. This waveform is deduced after careful and extensive study of the performance of these devices. The results presented here indicate the superiority of the performance of the IMPATTs driven by the proposed waveform over that obtained when the same IMPATTs are driven by the conventional sinusoidal waveform. These results are obtained using a full-scale computer simulation program that takes fully into account all the physical effects pertinent to IMPATT operation.  In this paper, it is indicated that the superiority of the proposed waveform is attributed to its ability to reduce the bad effects that usually degrade the IMPATT performance such as the space-charge effect and the drift-velocity dropping below saturation effect. The superiority is also attributed to the ability of the proposed waveform to improve the phase relationship between the terminal voltage and the induced current.Key Words: Computer-Aided Design, GaAs IMPATT, Microwave Engineering

scholarly journals Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example

Materials ◽  
2022 ◽  
Vol 15 (2) ◽  
pp. 457
Author(s):  
Zhaoxiang Wei ◽  
Hao Fu ◽  
Xiaowen Yan ◽  
Sheng Li ◽  
Long Zhang ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Impact Ionization ◽  
Field Effect Transistors ◽  
Vertical Channel ◽  
Ionization Rate ◽  
Oxide Semiconductor ◽  
Inclined Channel ◽  
Device Structures ◽  
Aided Design ◽  
Impact Ionization Rate

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

A Simulation Study on Reducing the Grain Boundary Position Dependency in Tunneling Thin-Film Transistors Using a Wide Tunneling Area

2020 ◽  
Vol 20 (11) ◽  
pp. 6627-6631
Author(s):  
Hyun-Min Kim ◽  
Junil Lee ◽  
Yunho Choi ◽  
Jong-Ho Lee ◽  
Byung-Gook Park
Keyword(s):  
Grain Boundary ◽  
Computer Aided Design ◽  
Deposition Process ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Limited Region ◽  
Layer Deposition ◽  
Boundary Position ◽  
Simulation Results ◽  
Aided Design

In this paper, we confirmed the effect of the grain boundary position dependency on short channel poly-Si Tunneling TFTs using technology computer aided design (TCAD) simulation. The simulation results show that the grain boundary (GB) in the channel affects the tunneling barrier and thus, produces variations in the electrical characteristics of the device such as the Vth and off-current. In the case of tunneling TFTs, the characteristics of the entire device are determined by the band to band tunneling (BTBT) currents occurring in very limited regions. In this study, we proposed that a TFT device requires a wider BTBT region because this limited region worsens the variations in the electrical characteristics of the TFT device. Two additional methods were proposed, one using vertical BTBT over a wide area through an additional poly-Si layer deposition and one widening the BTBT area through tilting implantation without an additional deposition process. The simulation results show that the variation of Vth is reduced to 10% through the extension of the BTBT area.

scholarly journals Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

2019 ◽  
Vol 8 (10) ◽  
pp. 393-396 ◽  
Keyword(s):  
Computer Aided Design ◽  
Gate Dielectric ◽  
Dielectric Materials ◽  
Electrical Characteristics ◽  
Back Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Low Power Logic ◽  
Aided Design ◽  
Tcad Simulations

In this paper, DC performance of double gate tunnel field effect transistor with heterojunction has been assessed by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Different hetero high-κ dielectric materials like HfO2 , ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using band to band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, attains maximum value of ION as 1.522 × 10-5 A/µm. The subthreshold swing (ss) has also been recorded best as 23.93 mV/dec in comparison with conventional homo dielectric i.e. SiO2 -SiO2 oxide throughout the 50 nm channel of HTFET as 34.22 mV/dec, can serve as better alternative tunnel FETs in low power logic applications.

Si1-yGeyor Ge1-zSnzSource/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

2013 ◽  
Vol 52 (4S) ◽  
pp. 04CC01 ◽  
Author(s):  
Geert Eneman ◽  
An De Keersgieter ◽  
Liesbeth Witters ◽  
Jerome Mitard ◽  
Benjamin Vincent ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Design Study ◽  
Computer Aided ◽  
P Type ◽  
Aided Design

scholarly journals F-Shaped Tunnel Field-Effect Transistor (TFET) for the Low-Power Application

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 760 ◽  
Author(s):  
Seunghyun Yun ◽  
Jeongmin Oh ◽  
Seokjung Kang ◽  
Yoon Kim ◽  
Jang Hyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Characteristics ◽  
Turn On ◽  
Crowding Effects ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Power Application ◽  
Aided Design

In this report, a novel tunnel field-effect transistor (TFET) named ‘F-shaped TFET’ has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As a result, it is compared to an L-shaped TFET, which is a motivation of this work, the F-shaped TFET can lower turn-on voltage (VON) maintaining high on-state current (ION) and low subthreshold swing (SS) with the help of electric field crowding effects. The optimized F-shaped TFET shows 0.4 V lower VON than the L-shaped TFET with the same design parameter. In addition, it shows 4.8 times higher ION and 7 mV/dec smaller average SS with the same VON as that for L-shaped TFET.

scholarly journals A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 164
Author(s):  
Ke Han ◽  
Shanglin Long ◽  
Zhongliang Deng ◽  
Yannan Zhang ◽  
Jiawei Li
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Source Voltage ◽  
Effect Transistor ◽  
Supply Current ◽  
Aided Design

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

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