Study of Warpage and Mechanical Stress of 2.5D Package Interposers during Chip and Interposer Mount Process

2012 ◽  
Vol 2012 (1) ◽  
pp. 000967-000974 ◽  
Author(s):  
Takashi Hisada ◽  
Yasuharu Yamada ◽  
Junko Asai ◽  
Toyohiro Aoki
Keyword(s):  
Mechanical Stress ◽  
Dielectric Layer ◽  
Coefficient Of Thermal Expansion ◽  
Transmission Rate ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Von Mises Stress ◽  
Design Elements ◽  
Plastic Ball ◽  
Low K

As data transmission rate increases, flip chip plastic ball grid array (FCPBGA) utilizing a interposer for multiple chips is gaining popularity because of high electrical performance, ease of chip design, ease of thermal management with thermal lid, etc. The authors assessed package design configuration and key design elements for two chips application assuming 1600 signal I/Os for logic and 800 signal I/Os for memory. Then, we studied warpage behavior of the interposer, and mechanical stress of solder interconnections and low-k dielectric layer under controlled collapse chip connection (C4) pad. We set three different mount process assumptions for chip to interposer and interposer to base organic substrate. The mount process assumptions are (1) two pass reflow of chip to interposer first, then interposer to base organic substrate, (2) reversed sequence of two pass reflow which is interposer to base organic substrate first, then chip to interposer, (3) one pass reflow of chip, interposer and base organic substrate all together. We also set three different interposer material assumptions of Si, glass and organic in this study. We analyzed warpage behavior and mechanical stress using finite element method (FEM) modeling technique with a set of combinations of coefficient of thermal expansion (CTE) and elastic modulus of the interposers. The study also includes an analysis for conventional multi-chip-module (MCM) FCPBGA as a reference. We show the analysis results of interposer warpage, first principal stress at low-k dielectric layer under C4 pad and von Mises stress at solder interconnections of chip joining and interposer joining.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Development of G-Helix Structure as Off-Chip Interconnect

2004 ◽  
Vol 126 (2) ◽  
pp. 237-246 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Mechanical Performance ◽  
Coefficient Of Thermal Expansion ◽  
Mechanical Analysis ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Package Weight ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

Electrical Performance of Advanced Surface Laminar Circuit in High-end FCBGA Applications

2011 ◽  
Vol 2011 (1) ◽  
pp. 000805-000812
Author(s):  
Makoto Shiroshita ◽  
Satoshi Nakamura ◽  
Kenji Terada ◽  
Kimihiro Yamanaka
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Signal Integrity ◽  
Electrical Performance ◽  
Power Integrity ◽  
Reflow Process ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Package Size ◽  
Semiconductor Chips ◽  
Low K

Advanced Surface Laminar Circuit (Adv-SLC) is a build-up substrate technology designed to satisfy the requirement of the most advanced semiconductor chips. Adv-SLC is featuring a low Coefficient of Thermal Expansion (CTE) of 10 ppm/degC that reduces the strain in the solder joints and Cu/low-k stacked structure of semiconductor chips during the reflow process, ensures the solder joint reliability, and protects internal delamination of the Cu/low-k stacked structure. This paper describes the power integrity and signal integrity of Adv-SLC and the capability to reduce total layer count with considering X-talk, to reduce package size, and to improve Power Integrity by using Adv-SLC.

Study of Electroplated Compliant G-Helix Chip-to-Substrate Interconnects

2003 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Lower Cost ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Cross Section Area ◽  
Section Area ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant G-Helix interconnect will have a total standoff height of 64 μm, radius of 36 μm and cross-section area of 93 μm2.

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

Studies of the Coefficient of Thermal Expansion of Low-k ILD Materials by X-Ray Reflectivity

2006 ◽  
Vol 914 ◽  
Author(s):  
George Andrew Antonelli ◽  
Tran M. Phung ◽  
Clay D. Mortensen ◽  
David Johnson ◽  
Michael D. Goodner ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Expansion ◽  
Coefficient Of Thermal Expansion ◽  
Chemical Vapor ◽  
Dielectric Materials ◽  
Free Standing ◽  
Dielectric Thin Films ◽  
X Ray ◽  
Chemical Vapor Deposited ◽  
Low K

AbstractThe electrical and mechanical properties of low-k dielectric materials have received a great deal of attention in recent years; however, measurements of thermal properties such as the coefficient of thermal expansion remain minimal. This absence of data is due in part to the limited number of experimental techniques capable of measuring this parameter. Even when data does exist, it has generally not been collected on samples of a thickness relevant to current and future integrated processes. We present a procedure for using x-ray reflectivity to measure the coefficient of thermal expansion of sub-micron dielectric thin films. In particular, we elucidate the thin film mechanics required to extract this parameter for a supported film as opposed to a free-standing film. Results of measurements for a series of plasma-enhanced chemical vapor deposited and spin-on low-k dielectric thin films will be provided and compared.

Electrical-Thermal-Reliability Co-Design for TSV-Based 3D-ICs

2015 ◽  
Author(s):  
Tiantao Lu ◽  
Ankur Srivastava
Keyword(s):  
Mechanical Stress ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Thermal Reliability ◽  
Conduction Path ◽  
Placement Problem ◽  
Thermal Profile ◽  
3D Ic ◽  
3D Ics ◽  
Simulation Based

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.

Process-Oriented Stress Modeling and Stress Evolution During Cu/Low-K BEOL Processing

2004 ◽  
Vol 812 ◽  
Author(s):  
Charlie Jun Zhai ◽  
Paul R. Besser ◽  
Frank Feustel
Keyword(s):  
Stress State ◽  
Mechanical Stress ◽  
Plane Stress ◽  
Cmos Technology ◽  
Film Deposition ◽  
Stress Evolution ◽  
Process Step ◽  
Dual Damascene ◽  
Process Oriented ◽  
Low K

AbstractThe damascene fabrication method and the introduction of low-K dielectrics present a host of reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of Cu lines. In order to capture the effect of individual process steps on the stress evolution in the BEoL (Back End of Line), a process-oriented finite element modeling (FEM) approach was developed. In this model, the complete stress history at any step of BEoL can be simulated as a dual damascene Cu structure is fabricated. The inputs to the model include the temperature profile during each process step and materials constants. The modeling results are verified in two ways: through wafer-curvature measurement during multiple film deposition processes and with X-Ray diffraction to measure the mechanical stress state of the Cu interconnect lines fabricated using 0.13um CMOS technology. The Cu line stress evolution is simulated during the process of multi-step processing for a dual damascene Cu/low-K structure. It is shown that the in-plane stress of Cu lines is nearly independent of subsequent processes, while the out-of-plane stress increases considerably with the subsequent process steps.

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