Large Form Factor Hybrid LGA Interconnects; Recent Applications and Technical Learning

2014 ◽  
Vol 2014 (1) ◽  
pp. 000550-000560 ◽  
Author(s):  
John Torok ◽  
Brian Beaman ◽  
William Brodsky ◽  
Shawn Canfield ◽  
Jason Eagle ◽  
...  
Keyword(s):  
Form Factor ◽  
System Integration ◽  
Mechanical Analysis ◽  
Electrical Performance ◽  
Bottom Surface ◽  
Printed Wiring Board ◽  
Module Design ◽  
External Cooling ◽  
Reliability Characteristics ◽  
Server Design

Recent high-end server design trends have continued to challenge electronic packaging engineers to design and integrate larger form factor land grid array (LGA) attached modules within their assemblies. These trends have included the application of larger, denser, organic packaged modules whose electrical performance and postencapsulation physical characteristics have been enabled by both the continued development of hybrid LGA connectors as well as new module actuation hardware designs. In this paper, we'll discuss these recent trends, including the specific technical attributes and challenges that need to be addressed to ensure a repeatable and reliable assembly design is developed. Initially, overviews of the latest connector and module design trends, including styles and physical sizes and their implications to the module's bottom surface metallurgy (BSM) flatness requirements, etc. are provided. Pursuant to this, recent system integration trending is reviewed; including both the module quantity per system assembly as well as module to module physical placements and how each of these impact printed wiring board (PWB) design (i.e., layer count, LGA site flatness, etc.) as well as the PWB assembly's solder processing characteristics (i.e., LGA pre- and post-solder attach contact co-planarity, etc.). Completing the application portion, is a description of some recent LGA actuation hardware and module external cooling apparatus designs (e.g., air-cooled heats sinks and water-cooling cold-plates and thermal interface materials (TIMs), etc.). The remaining portion of the paper is dedicated to the description of the mechanical analysis efforts completed to provide a fundamental understanding of the design's “as-assembled” attributes and a review of the associated evaluation completed to verify the integrated assembly's reliability characteristics. From the analysis methodology perspective, both the means of including each of the integrated assembly's key attributes (e.g., module mechanical construction and as encapsulated flatness, LGA contact compliance and stiffness as well as soldered contact coplanarity, TIM stiffness, actuation hardware, heat sink and cold-plate mechanical construction, etc.) and the resulting estimation of the predicted module internal TIM and hybrid-LGA's Pb-free soldered interface strains, actuation hardware stresses and LGA contact load variation are provided. Completing the discussion is a review of the variety of testing executed to validate the design's intended reliability. Included in this is a description of the test vehicle's design, the environmental stress testing conducted (i.e., mechanical pre-conditioning, accelerated thermal cycling (ATC), mixed flowing gas (MFG) and heat aging (HA), etc.) and the resulting data.

CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000916-000936
Author(s):  
Jemmy Sutanto ◽  
D. H. Kang ◽  
J. H. Yoon ◽  
K. S. Oh ◽  
Michael Oh ◽  
...  
Keyword(s):  
Form Factor ◽  
System Integration ◽  
Wire Bonding ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Face To Face ◽  
Parasitic Resistance ◽  
On Chip ◽  
Packaging Cost

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size > 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

Thermal and Mechanical Analysis of a Multichip Module

1992 ◽  
Vol 264 ◽  
Author(s):  
M. S. Hu
Keyword(s):  
High Speed ◽  
Mechanical Analysis ◽  
High Density ◽  
Electrical Performance ◽  
Multichip Module ◽  
Multichip Modules ◽  
Printed Wiring Board ◽  
Proper Design ◽  
Wiring Board ◽  
High Density Packaging

AbstractHigh speed, high density packaging requirements have made multichip modules (MCM) one of the most active areas of research in the electronic industry.High density printed wiring board (PWB) have low production cost and good electrical performance. However, the most questioned issue in application is the reliability. As a result, a thermal and mechanical analysis on a MCM has been conducted to understand its feasibility. The results indicate that with proper design, the components can operate under satisfactory conditions on PWB laminates.

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

Performance and Reliability Characteristics of 1200 V, 100 A, 200°C Half-Bridge SiC MOSFET-JBS Diode Power Modules

2010 ◽  
Vol 2010 (HITEC) ◽  
pp. 000289-000296 ◽  
Author(s):  
James D. Scofield ◽  
J. Neil Merrett ◽  
James Richmond ◽  
Anant Agarwal ◽  
Scott Leslie
Keyword(s):  
Selection Process ◽  
Free Module ◽  
Junction Temperature ◽  
Thermal Impedance ◽  
Power Module ◽  
Package Design ◽  
Module Design ◽  
Reliability Characteristics ◽  
Power Modules ◽  
Environmental Requirement

A custom multi-chip power module packaging was designed to exploit the electrical and thermal performance potential of silicon carbide MOSFETs and JBS diodes. The dual thermo-mechanical package design was based on an aggressive 200°C ambient environmental requirement and 1200 V blocking and 100 A conduction ratings. A novel baseplate-free module design minimizes thermal impedance and the associated device junction temperature rise. In addition, the design incorporates a free-floating substrate configuration to minimize thermal expansion coefficient induced stresses between the substrate and case. Details of the module design and materials selection process will be discussed in addition to highlighting deficiencies in current packaging materials technologies when attempting to achieve high thermal cycle life reliability over an extended temperature range.

Z-Interconnect Technology - A Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packaging

2014 ◽  
Vol 2014 (1) ◽  
pp. 000141-000147 ◽  
Author(s):  
John M. Lauffer ◽  
Kevin Knadle
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Performance Enhancement ◽  
High Density ◽  
Consumer Electronics ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Electrically Conductive Adhesive ◽  
Plated Through Hole ◽  
Interconnect Technology

Common themes across all segments of electronic packaging today are density and performance. High density interconnect (HDI) technology is one of the most commonly utilized methods for electronic package density improvement, while many different areas have been investigated for performance improvement, from low loss dielectric and conductor materials, to via design and via stub reduction. Electrical performance and density requirements are sometimes complementary, but often times, conflicting with one another. This paper will describe the design, materials, fabrication, and reliability of a new Z-Interconnect technology that addresses both high density and high performance demands simultaneously. Z-Interconnect technology uses an electrically conductive adhesive to electrically interconnect several cores (Full Z) or sub-composites (Sub Z) in a single lamination process. Z-Interconnect technology will be compared and contrasted to other commonly used solutions to the performance and density challenges. HDI or sequential build-up technology is a pervasive solution to the density demands in semiconductor packaging and consumer electronics (e.g. Smart phones), but has not caught hold in HPC or A&D printed wiring board (PWB) applications. One solution for PWB electrical performance enhancement is plated through hole (PTH) stub reduction by “back drilling” the unwanted portion of the PTH. Pb-free reflow and Current Induced Thermal Cycling (CITC) test results of product coupons and specially designed test vehicles, having component pitches down to 0.4mm, will be presented. Z-Interconnect test vehicles have survived 6X Pb-free (260C) reflow cycles, followed by greater than 3000 cycles of 23C–150C CITC cycles. Test vehicle and product coupons also easily survive 10 or more 23C–260C CITC cycles.

The Benefits of Flux-Coated Solder Preforms in a QFN Assembly Process

2015 ◽  
Vol 2015 (1) ◽  
pp. 000827-000832
Author(s):  
Brandon Judd ◽  
Maria Durham
Keyword(s):  
Mechanical Properties ◽  
Form Factor ◽  
Solder Joint ◽  
Circuit Board ◽  
Electrical Performance ◽  
Solder Paste ◽  
Assembly Process ◽  
Circuit Board Assembly ◽  
Difficult Challenge ◽  
Small Form Factor

The use of bottom terminated components (BTCs) such as quad-flat no-leads (QFNs) has become commonplace in the circuit board assembly world. This package offers several benefits including its small form factor, its excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. These components are generally attached to PWBs PCBs via solder paste. The design of these components with the large thermal pad, along with the tendency of solder paste to outgas during reflow from the volatiles in the flux, creates a difficult challenge in terms of voiding control within the solder joint. Voiding can have a serious effect on the performance of these components, including the mechanical properties of the joint as well as spot overheating. Solder preforms with a flux coating can be added to the solder paste to help reduce voiding. This study will focus on the benefits of utilizing solder preforms with modern flux coatings in conjunction with solder paste to help reduce voiding under QFNs, as well as the design and process parameters which provide optimal results.

Mechanical Stress Analysis and Evaluation of Hybrid Land Grid Array Attached Large Form Factor Organic Modules

2012 ◽  
Vol 2012 (1) ◽  
pp. 000818-000824
Author(s):  
John Torok ◽  
Shawn Canfield ◽  
Yuet-Ying Yu ◽  
Jiantao Zheng
Keyword(s):  
Form Factor ◽  
Stress Analysis ◽  
Mechanical Stress ◽  
Printed Circuit Board ◽  
Organic Substrate ◽  
Circuit Board ◽  
Bottom Surface ◽  
Mechanical Shock ◽  
Analysis And Evaluation ◽  
Pcb Assembly

Recent industry trends to continue enabling increased server system performance and packaging density has driven the need to implement larger form factor hybrid land grid array (LGA) attached organic modules. In addition, given the need to package multiple modules on a single printed circuit board (PCB) assembly, PCB cross-sections and their corresponding physical properties (e.g., flatness, etc.) as well as module bottom surface metallurgy (BSM) co-planarity require a more detailed understanding of impacts to the compliant as well as the soldered connector interfaces. Lastly, the migration to lead (Pb)-free solders has further complicated the issue given both the change in material properties as well as processing temperatures. In this paper we will discuss the mechanical stress analysis and evaluation tests assessment of a recently developed 50 mm square organic processor module, hybrid LGA attached to a multiple site PCB. The analysis presented will highlight the methodology to identify both connector soldered stress and predicted contact load variation across the module's mated interface. Key parameters discuss will include the PCB flatness, Organic substrate BSM co-planarity (both predicted and measured) and the Hybrid LGA as-soldered contact co-planarity. Corroborating predicted analytical results, we will discuss various evaluation tests performed to validate the design's integrity. Key tests include, pressure sensitive film (PSF) studies and environment stress exposures, including thermal shock, mechanical shock and vibration and seismic exposure. Post test electrical integrity and test sample construction analysis, including 3D x-ray and mechanical cross-section, will also be described. The analysis process and testing described will provide a method to evaluate more challenging hybrid LGA applications as both module sizes and/or number applied per PCB assembly increase and Pb-free assembly is introduced in future applications.

Development of G-Helix Structure as Off-Chip Interconnect

2004 ◽  
Vol 126 (2) ◽  
pp. 237-246 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Mechanical Performance ◽  
Coefficient Of Thermal Expansion ◽  
Mechanical Analysis ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Package Weight ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

A Novel Discrete Passives Integration on Organic Substrate

2005 ◽  
Author(s):  
Vasudivan Sunappan ◽  
Chee Wai Lu ◽  
Lai Lai Wai ◽  
Wei Fan ◽  
Boon Keng Lok
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Electrical Performance ◽  
Core Material ◽  
Bottom Surface ◽  
Passive Components ◽  
Printed Circuit

A novel process has been developed to embed discrete (surface mountable) passive components like capacitors, resistors and inductors using printed circuit board fabrication technology. The process comprises of mounting passive components on top surface of a core PCB (printed circuit board) material using surface mount technology. The passive components mounting were designed in multiple clusters within the PCB. Dielectric sheets are sandwiched between top surface of core PCB and second PCB material for lamination process. A direct interconnection of the passive components to one or more integrated circuits (IC) is further accomplished by mounting the ICs on the bottom surface of the core material in an area directly under the passive components. The close proximity of the embedded passive components such as capacitors to an IC improved electrical performance by providing impedance reduction and resonance suppression at high frequency range. The reliability of solder joints was evaluatedd by temperature cycling test.

Achieving Ceramic-like RF Capacitor Requirements with Organic-based Materials

2010 ◽  
Vol 2010 (1) ◽  
pp. 000072-000075 ◽  
Author(s):  
Jin-Hyun Hwang ◽  
John Andresakis ◽  
Bob Carter ◽  
Yuji Kageyama ◽  
Fujio Kuwako
Keyword(s):  
Dielectric Constant ◽  
Form Factor ◽  
High Dielectric Constant ◽  
High Volume ◽  
Electrical Performance ◽  
Frequency Range ◽  
Large Area ◽  
Low Loss ◽  
Capacitance Variation ◽  
High Dielectric

New and novel organic-based composite materials for the use of embedded RF capacitors have been developed to address the important material issues by means of functional filler and resin chemistry. Combining different fillers with appropriate chemistries, the net composite can be made thermally stable while retaining the high dielectric constant and low loss. These composites attained dielectric constant of above 7 without compromising the quality factor in GHz frequency range. In addition, measurement of capacitance variation as a function of temperature (TCC) showed flatter TCC profile, resulting in TCC of ±30 ppm/°C over the temperature range −55°C to 125°C. It can be incorporated into organic chip package and, unlike ceramic-based LTCC they can utilize large area processing that is typical, and available in high volume manufacturing. This material is formulated for RF module designers to successfully implement embedded RF capacitors into their organic chip package designs and thus improve form factor, electrical performance and possibly reduce overall costs.

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