scholarly journals Resolution of Damaged Metallization on Highly Complex Semiconductor Device

2020 ◽  
pp. 7-12
Author(s):  
Antonio Sumagpang Jr. ◽  
Frederick Ray Gomez
Keyword(s):  
Design Of Experiments ◽  
Semiconductor Device ◽  
Electrostatic Discharge ◽  
Test Design ◽  
Functional Testing ◽  
Assembly Process ◽  
Short Contact ◽  
Contact Test ◽  
Corrective Actions ◽  
Complex Semiconductor

The paper focused on the resolution of damaged metallization during assembly process that lead to gross open-short (O/S) rejections during functional testing of a highly complex semiconductor package. Numerous batches were put on hold due to not meeting the specification assigned for the short contact test. Design of experiments (DOE) on assembly processes were conducted and eventually identified the reject as an electrostatic discharge (ESD) related failure. Corrective actions and ESD controls significantly reduced the occurrence of damaged metallization with around 85% reduction.

scholarly journals Addressing Package Voids on Extremely Small Leadframe Device

2020 ◽  
pp. 1-7
Author(s):  
A. Sumagpang Jr. ◽  
F. R. Gomez
Keyword(s):  
Risk Analysis ◽  
Design Of Experiments ◽  
Potential Risk ◽  
Semiconductor Device ◽  
Curing Time ◽  
Molding Process ◽  
Robust Solution ◽  
Molding Temperature ◽  
Corrective Actions

The paper focused in addressing the package voids defect of a semiconductor device utilizing an extremely small leadframe technology. Potential risk analysis and pareto diagram were completed to identify the top reject contributors and eventually come-up with the robust solution. A comprehensive design of experiments (DOE) was completed and solution validation was performed to formulate the effective corrective actions. Results revealed that package voids were addressed by optimizing the molding process focusing on the molding temperature and curing time. A significant improvement of 95 % for package voids reduction was achieved. For future works, the parameters and learnings could be used on devices with similar configuration.

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

scholarly journals Improvement on Leakage Current Performance of Semiconductor IC Packages by Eliminating ESD Events

2018 ◽  
Vol 6 (5) ◽  
Author(s):  
Frederick Ray Gomez
Keyword(s):  
Product Quality ◽  
Leakage Current ◽  
Integrated Circuit ◽  
Six Sigma ◽  
Electrostatic Discharge ◽  
Assembly Process ◽  
Technical Paper ◽  
High Leakage Current ◽  
Better Than

The technical paper discusses the reduction of high leakage current failures of semiconductor IC (integrated circuit) packages by eliminating the ESD (electrostatic discharge) events during assembly process and ensuring the appropriate machine grounding and ESD controls.  It is imperative to reduce or ideally eliminate the leakage current failures of the device to ensure the product quality, especially as the market becomes more challenging and demanding.  After implementation of the corrective and improvement actions, high leakage current occurrence was reduced from baseline of 5784 ppm to 1567 ppm, better than the six sigma goal of 4715 ppm.

A Methodology for Addressing Defects in Transfer Moulding as an Encapsulating Technique for Semi-Conductors

2014 ◽  
Author(s):  
Philip Farrugia ◽  
Pierre Vella ◽  
Godwin Cutajar Kinsella
Keyword(s):  
Semiconductor Device ◽  
Semiconductor Devices ◽  
Die Design ◽  
Design Decision ◽  
Integrated Product Development ◽  
Execution Phase ◽  
Preparation Phase ◽  
Production Preparation ◽  
Transfer Moulding ◽  
Complex Semiconductor

One of the manufacturing steps involved in fabricating semiconductor devices is encapsulation, whose function is to protect the semiconductor device by sealing the package from environmental hazards such as heat, humidity and vibration. Transfer moulding, as an encapsulation technique, offers various advantages over other techniques such as injection moulding. In most cases it is difficult to foresee the effect of a design decision on a complex semiconductor process such as transfer moulding, since process robustness is rarely a function of a single property and is affected by several different parameters. A literature review reveals that whilst support has been developed to help relevant stakeholders to detect and rectify problems associated with fabrication of semiconductors, such as die design, photolithography and ion implantation, support aimed at guiding process engineers and other relevant stakeholders to rapidly deal with transfer moulding defects, are lacking. Within this context, the research reported in this paper is aimed at developing a methodology relevant to transfer moulding which guides stakeholders in identifying and rectifying mouldability problems concerning new semiconductor devices. The proposed methodology is aimed at capitalizing efforts on the production preparation phase of the Integrated Product Development model before problematic semiconductor products reach the execution phase. The methodology is the key contribution of this paper. The evaluation results collectively provide a degree of evidence that the developed methodology helps relevant stakeholders in this direction.

DESIGN CONCEPT OF MOBILE STATIC DISCHARGER FOR HUMAN BODY ELECTROSTATIC DISCHARGE USING VAN DE GRAAFF’S GENERATORtic Discharge Using Van de Graaff’s Generator

2015 ◽  
Vol 78 (1) ◽  
Author(s):  
Soo King Lim ◽  
Chong Yu Low ◽  
Koon Chun Lai
Keyword(s):  
Conceptual Design ◽  
Human Body ◽  
Semiconductor Manufacturing ◽  
Literature Search ◽  
Negative Charge ◽  
Semiconductor Device ◽  
Electrostatic Discharge ◽  
Semiconductor Industry ◽  
Charge Cloud ◽  
Process Damage

The damage of electrostatic discharge (ESD) is a well-known problem in the semiconductor industry. When human body (operator) is in contact with electrostatic sensitive semiconductor device during manufacturing process, damage to the oxide and other active parts of the device is caused by transferring of charge between device and human body. Semiconductor industry adopts preventive and protective approaches by grounding the human body with a wrist strap connecting to utility ground to neutralize the charge and setting up ESD preventive and protective workstation. Wearing a wrist strap is impractical for the operator and it causes psychological effect as the operator would not like to be strapped. A literature search and visit of many large semiconductor manufacturing facilities have revealed that there is no alternative mean used to neutralize charge from human body besides wearing a wrist strap. This paper presents a conceptual design of a mobile static discharger for human body electrostatic discharge using Van de Graaff’s generator to generate equal amount of positive and negative charge cloud to neutral the charge of the operator. The conceptual design is a fool-proof design and it is viable to be implemented. It is also a design that will revolutionize the technique of electrostatic discharge for human body in the semiconductor industry.

Defects in β-SiC thin films grown on α-SiC substrates

1988 ◽  
Vol 46 ◽  
pp. 568-569
Author(s):  
Karren L. More
Keyword(s):  
Thin Films ◽  
Semiconductor Device ◽  
Lattice Mismatch ◽  
Chemical Vapor ◽  
Substrate Material ◽  
Growth Interface ◽  
Si Substrates ◽  
Thermal Expansion Coefficients ◽  
Device Applications ◽  
Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

Applications of SIMS to electronic materials and devices

1992 ◽  
Vol 50 (2) ◽  
pp. 1682-1683
Author(s):  
S.F. Corcoran
Keyword(s):  
Depth Distribution ◽  
Secondary Ion Mass Spectrometry ◽  
Semiconductor Device ◽  
Electronic Materials ◽  
Profile Analysis ◽  
Semiconductor Industry ◽  
Small Diameter ◽  
Depth Resolution ◽  
Detection Sensitivity

Over the past decade secondary ion mass spectrometry (SIMS) has played an increasingly important role in the characterization of electronic materials and devices. The ability of SIMS to provide part per million detection sensitivity for most elements while maintaining excellent depth resolution has made this technique indispensable in the semiconductor industry. Today SIMS is used extensively in the characterization of dopant profiles, thin film analysis, and trace analysis in bulk materials. The SIMS technique also lends itself to 2-D and 3-D imaging via either the use of stigmatic ion optics or small diameter primary beams.By far the most common application of SIMS is the determination of the depth distribution of dopants (B, As, P) intentionally introduced into semiconductor materials via ion implantation or epitaxial growth. Such measurements are critical since the dopant concentration and depth distribution can seriously affect the performance of a semiconductor device. In a typical depth profile analysis, keV ion sputtering is used to remove successive layers the sample.

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