Mechanical and Electrical Study of Linear Spring and J-Spring

2002 ◽  
Author(s):  
Lunyu Ma ◽  
Qi Zhu ◽  
Suresh K. Sitaraman
Keyword(s):  
Integrated Circuit ◽  
Numerical Models ◽  
Low Cost ◽  
Stress Gradient ◽  
Electrical Characteristics ◽  
Wafer Level ◽  
Technology Roadmap ◽  
Linear Spring ◽  
Compliant Interconnect ◽  
Institute Of Technology

The integrated circuit (IC) fabrication technology continues to push the limits of microelectronics packaging technologies. Today millions of transistors can be fabricated in a chip of about 1 cm × 1 cm in size, and the required I/O density is about 1600/cm2. Although tremendous advances have been made in die to substrate interconnect technologies as well as substrate/PWB technologies, these advances have not kept pace with advances in semiconductor technology, and therefore, continue to be a bottleneck for further advances in semiconductor technologies. In addition to fabrication constraints, low cost and reliability are other requirements that affect interconnect development. Wafer-level Packaging (WLP) is an effective solution to address some of these issues. A compliant interconnect, called “J-Spring”, has been proposed and developed at Georgia Institute of Technology. Although based on the same concept of inherent stress-gradient used in the linear spring, the J-Spring will provide greater in-plane compliance. These compliant interconnects can be fabricated in batch at wafer level and the pitch can be as low as 30 μm. The fine pitch can meet and exceed the requirements of International Technology Roadmap for Semiconductor (ITRS) for 2011 [ITRS, 2001] and beyond. J-Springs with different radius, angle, width, and release length have been fabricated on a test wafer. Numerical model has been created to determine the release height based on J-Spring geometry and stress gradients. Also, the compliance of J-Spring has been determined in three orthogonal directions using parametric numerical models. The compliance of J-Spring is compared with the compliance of the linear spring. The proposed compliant interconnects can accommodate the differential displacement due to CTE mismatch between the die and the substrate. In addition, to their mechanical characteristics, their electrical characteristics have been studied as well. The electrical characteristics are dependent on the geometry, dimensions and the materials used.

Contact Reliability of Innovative Compliant Interconnects for Next Generation Electronic Packaging

2003 ◽  
Author(s):  
Lunyu Ma ◽  
Qi Zhu ◽  
Suresh K. Sitaraman
Keyword(s):  
Numerical Models ◽  
Research Work ◽  
Assembly Process ◽  
Contact Interface ◽  
Wafer Level ◽  
Ongoing Research ◽  
Fully Integrated ◽  
Compliant Interconnect ◽  
Institute Of Technology ◽  
The Cost

The ongoing research work at Georgia Institute of Technology, PARC, Inc., and Nanonexus, Inc. funded by NIST/ATP, aims to develop a novel compliant interconnect technology based on stress-engineering of thin-film metal deposition. The minimum pitch size can reach as small as 6 μm. The fabrication of the stress-engineered compliant interconnect is compatible with the standard IC fabrication processes. Therefore, the compliant interconnect fabrication can be fully integrated into front-end semiconductor process. Also, thousands of interconnects can be fabricated on the wafer in one batch, which can greatly reduce the cost, improve the yield, and facilitate wafer level packaging (WLP). Based on the mechanical advantage of the stress-engineered compliant interconnect, a non-soldering assembly process has been developed. In the non-soldering assembly process, compliant interconnects are pressed against the bonding pads to establish the electrical connection. Test vehicles with such non-soldering contact interconnect have been assembled and subjected to thermal cycling. Although the assembled test vehicles have shown reliability over 1000 cycles, the primary mode of failure occurs at the contact interface between the compliant interconnect tip and the bonding pad. This contact interface is studied using analytical and numerical models to understand the reliability of freestanding sliding-contact compliant interconnect assembly.

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

Compliant Stress-Engineered Interconnects for Next-Generation Packaging

2004 ◽  
Author(s):  
Kevin M. Klein ◽  
Suresh K. Sitaraman
Keyword(s):  
Life Stress ◽  
Low Cost ◽  
Intrinsic Stress ◽  
Wafer Level ◽  
Element Analysis ◽  
Operational Conditions ◽  
Technology Roadmap ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Future Demands

Future demands of microelectronic packing include increasing input/output (I/O) densities, providing high frequency capabilities, and maintaining sufficient reliability while keeping costs minimal. Organic materials with Coefficients of Thermal Expansions (CTE) over four times greater than silicon will continue to be used as future substrate materials because of their low cost. Consistent with the International Technology Roadmap for Semiconductors (ITRS, 2003), chip-to-substrate interconnects will need to have a pitch approximately equal to 40μm by the year 2012 and be able to accommodate the silicon and organic CTE mismatch without resorting to expensive reliability solutions. The demand for fine pitch chip-to-substrate interconnects combined with the CTE mismatch, creates significant demands for overall interconnect compliance as means to ensure reliability, through increasing fatigue life. Stress-engineered compliant off-chip interconnects are capable meeting future interconnect demands. Such interconnects are fabricated from stress-engineered metal thin-films using traditional IC fabrication methods and can be integrated with wafer level packing. A systematic design approach has been used to optimize interconnect geometry for use with estimated operational conditions. Finite Element Analysis (FEA) and Regression modeling have been used to create macro-models of interconnect behavior to assist in the optimization of the geometric design. Copper and Copper-Molybdenum are considered as interconnect material and the development intrinsic stress within copper is investigated via sputter deposition.

Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu IC’s

2006 ◽  
Author(s):  
Karan Kacker ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Dielectric Material ◽  
Semiconductor Industry ◽  
Cost Effective ◽  
Organic Substrate ◽  
Integrative Approach ◽  
Wafer Level ◽  
Technology Roadmap ◽  
Cte Mismatch ◽  
Compliant Interconnect ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

2014 ◽  
Vol 136 (2) ◽  
Author(s):  
Peisheng Liu ◽  
Jinlan Wang ◽  
Liangyu Tong ◽  
Yujuan Tao
Keyword(s):  
Integrated Circuit ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
3D Packaging ◽  
Circuit Fabrication ◽  
Fast Development ◽  
Small Form Factor

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

Wafer Level Integration of MMIC and Microwave IPD with Metal/BCB Multilayer Interconnection Based on Low Resistance Silicon

2011 ◽  
Vol 2011 (1) ◽  
pp. 001067-001073
Author(s):  
Jiajie Tang ◽  
Le Luo
Keyword(s):  
Silicon Wafer ◽  
Integrated Circuit ◽  
Performance Test ◽  
Low Cost ◽  
Cost Effective ◽  
Film Deposition ◽  
Thermal Dissipation ◽  
Shielding Effect ◽  
Wafer Level ◽  
Expansion Matching

A new high-density wafer-level integration of a GaAs based monolithic microwave integrated circuit (MMIC) chip and a microwave integrated passive device (IPD) is presented. This integration technology, an important and IC-compatible option for system-in-package (SiP), utilizes bulk Si fabrication and film deposition based multichip module (MCM-D) process. MMIC is entirely embedded into the silicon wafer while IPDs are integrated on the dielectric layers simultaneously with the metal/BCB multilayer interconnection. Key fabrication processes and crucial technologies are described in detail. Normal silicon wafer is selected as substrate because of its mature processing technology, low cost, good thermal dissipation as well as its thermal expansion matching with GaAs. To obtain excellent microwave performances and good planarization, thick photosensitive BCB of 25um/layer is adopted as dielectric and thus the use of tapered via that is hollow inside or filled by BCB is a cost-effective way to accomplish inter-layer connection instead of Au bump bonding or column used in dry-etch BCB process. Further promotions on microwave performances are achieved by the shielding effect through ground layer coverage on silicon surface and the application of microstrip lines. Several experiment results such as dc inter-layer connection resistance and thermal resistance measurements are complemented to investigate the characteristic of the whole package. The Microwave properties of the integration sample are measured by transmission performance test from 15GHz to 30GHz. The measurement results are analyzed and discussed comparing with the theoretical or simulation results.

Energy Analysis of Solar Home Lighting System With Microcontroller-Based Charge Controller

2014 ◽  
Vol 136 (3) ◽  
Author(s):  
Ashutosh S. Werulkar ◽  
P. S. Kulkarni
Keyword(s):  
Integrated Circuit ◽  
Liquid Crystal Display ◽  
Circuit Simulation ◽  
Low Cost ◽  
Simulation Software ◽  
Energy Gain ◽  
Solar Panel ◽  
Lighting System ◽  
Institute Of Technology ◽  
Gain Loss

In this paper, a solar powered home lighting system in the Electrical Engineering Department of Visvesvaraya National Institute of Technology (VNIT), Nagpur is analyzed for energy using a personal computer simulation program with integrated circuit emphasis (circuit simulation software, PSpice 9.1). The home lighting system consists of a solar panel of 37 Wp, a 45 Ah battery, a solar charge controller, dc loads of two 9 W compact fluorescent lamps (CFLs), and a dc fan of 14 W. Through the solar panel, the battery is charged during day time. In the night, when solar power is not available, the battery provides power as a backup to the dc load consisting of two CFLs and a dc fan. The aim of the paper is to analyze the solar home lighting system for energy gain/loss with a microcontroller-based charge controller. From the analysis, it is concluded that the solar home lighting system is not designed for continuous energy gain as per manufacturer's specifications. The design needs to be modified to have energy gain in the system for Nagpur, India. A designed microcontroller-based charge controller is also analyzed. The advantages of a microcontroller 89C2051-based charge controller are its simple design, low cost, logic change facility with change of programming of microcontroller, presence of liquid crystal display (LCD) with battery charge status, and display of different messages. Ride software is used as an assembler for generating the required hex file of program and it is used for burning in the microcontroller IC with the help of Vegarobokit (a microcontroller programmer developer) to make a microcontroller programmer.

Three-Mask Fabrication and Optimized Design of First-Level Free-Standing Interconnect for Microelectronics Application

2003 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Analytical Models ◽  
Optimized Design ◽  
Wafer Level ◽  
Free Standing ◽  
Mechanical Compliance ◽  
Compliant Interconnect ◽  
Free Solder

Advances in compliant off-chip interconnects have achieved great strides. G-Helix, an electroplated compliant chip-to-substrate interconnect has the potential for accomplishing low-cost, easy-to-fabricate, wafer-level packaging. In this work, the design, fabrication, optimization and reliability of the G-Helix compliant off-chip interconnects have been studied. A three-mask process was used to successfully fabricate the free-standing G-Helix compliant interconnect. The mechanical compliance and the electrical parasitics were studied through numerical and analytical models. Response Surface Methodology (RSM) was used to maximize the mechanical compliance and minimize the electrical parasitics as well as the stresses induced in the interconnect. It is also seen through the models that an array of interconnects will be able to withstand the die and the heat-sink weight without plastically yielding. Also, the G-Helix interconnect assembly on organic printed circuit board using lead-free solder will be able to withstand more than 1000 accelerated thermal cycles without the need for an underfill.

Programmable Integrated Photonics

2020 ◽  
Author(s):  
José Capmany ◽  
Daniel Pérez
Keyword(s):  
Integrated Circuit ◽  
Performance Monitoring ◽  
Low Cost ◽  
Limiting Factors ◽  
External Control ◽  
Integrated Photonics ◽  
New Paradigm ◽  
Photonic Integrated Circuit ◽  
And Performance ◽  
Application Fields

Programmable Integrated Photonics (PIP) is a new paradigm that aims at designing common integrated optical hardware configurations, which by suitable programming can implement a variety of functionalities that, in turn, can be exploited as basic operations in many application fields. Programmability enables by means of external control signals both chip reconfiguration for multifunction operation as well as chip stabilization against non-ideal operation due to fluctuations in environmental conditions and fabrication errors. Programming also allows activating parts of the chip, which are not essential for the implementation of a given functionality but can be of help in reducing noise levels through the diversion of undesired reflections. After some years where the Application Specific Photonic Integrated Circuit (ASPIC) paradigm has completely dominated the field of integrated optics, there is an increasing interest in PIP justified by the surge of a number of emerging applications that are and will be calling for true flexibility, reconfigurability as well as low-cost, compact and low-power consuming devices. This book aims to provide a comprehensive introduction to this emergent field covering aspects that range from the basic aspects of technologies and building photonic component blocks to the design alternatives and principles of complex programmable photonics circuits, their limiting factors, techniques for characterization and performance monitoring/control and their salient applications both in the classical as well as in the quantum information fields. The book concentrates and focuses mainly on the distinctive features of programmable photonics as compared to more traditional ASPIC approaches.

scholarly journals An Alternative Statistical Model for Predicting Salinity Variations in Estuaries

2020 ◽  
Vol 12 (24) ◽  
pp. 10677
Author(s):  
Ronghui Ye ◽  
Jun Kong ◽  
Chengji Shen ◽  
Jinming Zhang ◽  
Weisheng Zhang
Keyword(s):  
Statistical Model ◽  
River Discharge ◽  
Numerical Models ◽  
Low Cost ◽  
River Estuary ◽  
Pearl River Estuary ◽  
Large River ◽  
Physical Models ◽  
Long Term Effects ◽  
Salinity Variations

Accurate salinity prediction can support the decision-making of water resources management to mitigate the threat of insufficient freshwater supply in densely populated estuaries. Statistical methods are low-cost and less time-consuming compared with numerical models and physical models for predicting estuarine salinity variations. This study proposes an alternative statistical model that can more accurately predict the salinity series in estuaries. The model incorporates an autoregressive model to characterize the memory effect of salinity and includes the changes in salinity driven by river discharge and tides. Furthermore, the Gamma distribution function was introduced to correct the hysteresis effects of river discharge, tides and salinity. Based on fixed corrections of long-term effects, dynamic corrections of short-term effects were added to weaken the hysteresis effects. Real-world model application to the Pearl River Estuary obtained satisfactory agreement between predicted and measured salinity peaks, indicating the accuracy of salinity forecasting. Cross-validation and weekly salinity prediction under small, medium and large river discharges were also conducted to further test the reliability of the model. The statistical model provides a good reference for predicting salinity variations in estuaries.

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