scholarly journals Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 913
Author(s):  
Donglin Zhang ◽  
Bo Peng ◽  
Yulin Zhao ◽  
Zhongze Han ◽  
Qiao Hu ◽  
...  
Keyword(s):  
Random Access ◽  
Cmos Technology ◽  
Resistive Random Access Memory ◽  
Advanced Technology ◽  
Access Time ◽  
The Novel ◽  
Application Range ◽  
Design And Optimization ◽  
Technology Nodes ◽  
Novel Design

Resistive random access memory (RRAM) is one of the most promising new nonvolatile memories because of its excellent properties. Moreover, due to fast read speed and low work voltage, it is suitable for seldom-write frequent-read applications. However, as technology nodes shrink, RRAM faces many issues, which can significantly degrade RRAM performance. Therefore, it is necessary to optimize the sensing schemes to improve the application range of RRAM. In this paper, the issues faced by RRAM in advanced technology nodes are summarized. Then, the advantages and weaknesses in the novel design and optimization methodologies of sensing schemes are introduced in detail from three aspects, the reference schemes, sensing amplifier schemes, and bit line (BL)-enhancing schemes, according to the development of technology in especially recent years, which can be the reference for designing the sensing schemes. Moreover, the waveforms and results of each method are illustrated to make the design easy to understand. With the development of technology, the sensing schemes of RRAM become higher speed and resolution, low power consumption, and are applied at advanced technology nodes and low working voltage. Now, the most advanced nodes the RRAM applied is 14 nm node, the lowest working voltage can reach 0.32 V, and the shortest access time can be only a few nanoseconds.

scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

The Growth of Advanced Packaging: An Overview of the Latest Technology Developments, Applications and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000001-000005 ◽  
Author(s):  
R. Beica ◽  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
J. Azemar
Keyword(s):  
Semiconductor Industry ◽  
Cost Effective ◽  
Cmos Technology ◽  
Advanced Technology ◽  
Current Trends ◽  
Advanced Packaging ◽  
Scaling Process ◽  
Market Trends ◽  
The Cost ◽  
Technology Nodes

The semiconductor industry, for more than five decades, has followed Moore's law and was driven by miniaturization of the transistors, scaling the CMOS technology to smaller and more advanced technology nodes while, at the same time, reducing the cost. The industry is reaching now limitations in continuing this scaling process in cost effective way. While technology nodes continue to be developed and innovative solutions are being proposed, the investment required to bring such technologies to production are significantly increasing. To overcome these limitations, new packaging technologies have been developed, enabling integration of more performing as well as various type of devices within the same package. This paper will provide an overview of current trends seen in the industry across all the packaging platforms (WLCSP1, FanOut2, Embedded Die2, Flip Chip3 and 3DIC4). Challenges, applications, positioning of the different packaging technologies by market segments (from low end to high end applications) and changes of the markets and drivers, growth rates and roadmaps will be presented. Global capacities and demands and the landscape of the packaging industry will be reviewed. Examples of teardowns to illustrate the latest packaging techniques for various devices used in latest products will be included.

Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology

MRS Advances ◽  
2019 ◽  
Vol 4 (48) ◽  
pp. 2577-2584
Author(s):  
James N. Pan
Keyword(s):  
Quantum Wells ◽  
High Frequency ◽  
Nonvolatile Memory ◽  
High Speed ◽  
Random Access ◽  
Cost Effective ◽  
Cmos Technology ◽  
Access Time ◽  
Cmos Process ◽  
Atomic Force

ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

scholarly journals Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Muhammad Ovais Akhter ◽  
Najam Muhammad Amin
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
High Gain ◽  
The Novel ◽  
Ultra Low Power ◽  
Design And Optimization ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Insertion Losses

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

scholarly journals Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

2014 ◽  
Vol 68 (3) ◽  
Author(s):  
Nor Zaidi Haron ◽  
Norsuhaidah Arshad ◽  
Fauziyah Salehuddin
Keyword(s):  
Performance Analysis ◽  
Defect Density ◽  
Random Access ◽  
Cmos Technology ◽  
Resistive Random Access Memory ◽  
Cell Array ◽  
Access Memory ◽  
Sense Amplifier ◽  
Emerging Memory ◽  
Initial Work

Resistive Random Access Memory (RRAM) is gaining attention as one of the prominent contenders to replace the conventional memory technologies such as SRAM, DRAM and Flash. This emerging memory uses scaled CMOS devices (22 nm or less) to form the peripheral circuits such as decoder and sense amplifier; while a non-CMOS device known as memristor is used to form the cell array. Although potentially becoming the main future memory, RRAM is anticipated to be impacted by the high manufacturing defect density that in turn might lead to quality and reliability problems. This paper presents the initial work towards producing a high quality and reliable RRAM devices. A design and simulation of three memristor SPICE models published in prominent literatures were performed using Silvaco EDA simulation tool. The aim is to identify the optimal model to be used in our RRAM design, which is based on 22 nm CMOS technology. Performance analysis shows that the model proposed by D. Biolek is suitable to be used in our RRAM design.

Conductive-AFM for Scan Logic Failure Analysis at Advanced Technology Nodes

2016 ◽  
Author(s):  
Chuan Zhang ◽  
Oh Chong Khiam ◽  
Esther P.Y. Chen
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Leading Edge ◽  
Advanced Technology ◽  
The Novel ◽  
Conductive Atomic Force Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
Technology Nodes ◽  
Process Structure

Abstract The increase in complexity of process, structure, and design not only increases the amount of failure analysis (FA) work significantly, but also leads to more complicated failure modes. To meet the need of high success rate and fast throughput FA operation at the leading-edge nodes, novel FA techniques have to be explored and incorporated into the routine FA flow. One of the novel techniques incorporated into the presented scan logic FA flow is the conductive-atomic force microscopy (CAFM) technique. This paper demonstrates CAFM technique as a powerful and efficient solution for scan logic failure analysis at advanced technology nodes. Several failure modes in scan logic FA are used as examples to illustrate how CAFM provides excellent solutions to some of the very challenging FA problems. The gate to active short in nFET devices, resistive contact, and open defect on gate contact are some modes used.

Time-Domain Readout of 1T–1C DRAM Cells

2017 ◽  
Vol 27 (01) ◽  
pp. 1850005 ◽  
Author(s):  
Sherif M. Sharroush
Keyword(s):  
Time Domain ◽  
Noise Analysis ◽  
Average Power ◽  
Random Access ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Access Time ◽  
Technology Scaling ◽  
Sense Amplifier ◽  
Power Delay Product

The conventional readout of one-transistor–one-capacitor dynamic random-access memories (1T–1C DRAMs) depends on using a sense amplifier to develop the bitline voltage and settle it to the voltage of the power supply, [Formula: see text], or to 0[Formula: see text]V depending on whether the stored data is “1” or “0,” respectively. However, using the sense amplifier makes the reading process sluggish. In this paper, a capacitive-voltage divider-based readout scheme is proposed. According to this scheme, the developed bitline voltage is converted into a pulse with a certain starting time. Specifically, this pulse appears at a later time in case of “0” storage than that if a “1” is stored, thus the proposed scheme is aptly called “time-domain readout.” The effects of parameter and component mismatches and technology scaling on the proposed scheme are investigated. The proposed scheme is analyzed quantitatively with a suggestion given to widen the time gap between the starting times of the pulses corresponding to the “0” and “1” states. The proposed scheme is verified by simulation adopting the 45 nm CMOS technology with [Formula: see text][Formula: see text]V. According to the simulation results, percentage savings of 68.8%, 56.8%, and 32% in the read-access time, the read-cycle time, and the average power-delay product, respectively, are shown. The proposed scheme requires approximately 40% extra area overhead for the reading circuitry. Also, a noise analysis is performed and it is found that the device noise does not affect the proposed scheme significantly.

scholarly journals Design of Efficient, Dependable SoCs Based on a Cross-Layer-Reliability Approach with Emphasis on Wireless Communication as Application and DRAM Memories

2020 ◽  
pp. 435-455
Author(s):  
Christian Weis ◽  
Christina Gimmler-Dumont ◽  
Matthias Jung ◽  
Norbert Wehn
Keyword(s):  
Mimo System ◽  
Random Access ◽  
Error Resilience ◽  
Advanced Technology ◽  
Cross Layer ◽  
Multiple Antenna ◽  
Error Resilient ◽  
Reliability Management ◽  
Inherent Error ◽  
Technology Nodes

AbstractMany applications show an inherent error resilience due to their probabilistic behavior. This inherent error resilience can be exploited to reduce the design margin for advanced technology nodes resulting in more energy and area efficient implementation. We present in this chapter a cross-layer approach for efficient reliability management in wireless baseband processing with special emphasis on memories since memories are most susceptible to dependability problems. A multiple-antenna (MIMO) system will be used as design example. Further on we focus on DRAMs (Dynamic Random Access Memories). All today’s computing systems rely on dependable DRAMs. In the future DRAM memories will become more undependable due to further scaling. This has to be counterbalanced with higher refresh rates, which leads to a higher DRAM power consumption. Recent research activities resulted in the concept of “approximate DRAM” to save power and improve performance by lowering the refresh rate or disabling refresh completely. Here, we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error-resilient applications.

scholarly journals Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory

Materials ◽  
2019 ◽  
Vol 12 (21) ◽  
pp. 3461 ◽  
Author(s):  
Paolo La Torraca ◽  
Francesco Maria Puglisi ◽  
Andrea Padovani ◽  
Luca Larcher
Keyword(s):  
Neural Networks ◽  
Multiscale Modeling ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Promising Alternative ◽  
Von Neumann ◽  
Design And Optimization ◽  
Physical Mechanisms

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many different physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diffusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material’s microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device’s performance and variability to be evaluated, the analog resistance switching to be optimized, and the device’s reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.

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