Improved Evaluation Method for Channel Mobility in SiC Trench MOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 757-760 ◽  
Author(s):  
Katsuhiro Kutsuki ◽  
Sachiko Kawaji ◽  
Yukihiko Watanabe ◽  
Shinichiro Miyahara ◽  
Jun Saito
Keyword(s):  
Evaluation Method ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Effective Field ◽  
Channel Mobility ◽  
Definition Of ◽  
Effective Channel ◽  
Dominant Influence ◽  
The Ideal

We proposed an improved method for evaluating the effective channel mobility (μeff), involving an appropriate definition of the threshold voltage (Vth) based on the ideal gate bias voltage – drain current (VG-ID) characteristics. Using this method, the dependence of μeff on the effective field (Eeff) could be evaluated even for SiC trench MOSFETs with large interface state density (Dit) values. The dominant influence on μeff in the low Eeff region was found to be Coulomb scattering caused by interface states at the SiC/SiO2 interfaces.

MOS Interface Properties and MOSFET Performance on 4H-SiC{0001} and Non-Basal Faces Processed by N2O Oxidation

2004 ◽  
Vol 815 ◽  
Author(s):  
T. Kimoto ◽  
Y. Kanzaki ◽  
M. Noborio ◽  
H. Kawano ◽  
H. Matsunami
Keyword(s):  
Doping Concentration ◽  
Interface State ◽  
Interface Structure ◽  
State Density ◽  
Interface State Density ◽  
Interface Properties ◽  
Crystal Face ◽  
Channel Mobility ◽  
Pile Up ◽  
Effective Channel

Abstract4H-SiC(0001), (000-1), and (11-20) have been directly oxidized by N2O at 1300°C, and the MOS interfaces have been characterized. The interface state density has been significantly reduced by N2O oxidation on any face, compared to conventional wet O2 oxidation at 1150°C. Planar n-channel MOSFETs fabricated on lightly-doped 4H-SiC(0001), (000-1) and (11-20) faces have shown an effective channel mobility of 26, 43, and 78 cm2/Vs, respectively. The mobility decreased with increasing the doping concentration of p-body. SIMS analyses have revealed a clear pile-up of nitrogen atoms near the MOS interface. The thickness of interfacial SiCxOy layer can be decreased by utilizing N2O oxidation. The crystal face dependence of interface structure is discussed.

scholarly journals Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1858
Author(s):  
Matthew Whiteside ◽  
Subramaniam Arulkumaran ◽  
Yilmaz Dikme ◽  
Abhinay Sandupatla ◽  
Geok Ing Ng
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
High Electron Mobility Transistors ◽  
Interface State ◽  
State Density ◽  
High Electron ◽  
Gate Leakage ◽  
Annealing Effects ◽  
Low Temperature Epitaxy

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

scholarly journals Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations

2019 ◽  
Vol 114 (24) ◽  
pp. 242101 ◽  
Author(s):  
Tsubasa Matsumoto ◽  
Hiromitsu Kato ◽  
Toshiharu Makino ◽  
Masahiko Ogura ◽  
Daisuke Takeuchi ◽  
...  
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Channel Mobility ◽  
Inversion Channel

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

Analysis of Interface Trap Density and Channel Mobility in 4H-SiC NMOS Capacitors and Lateral MOSFETs

2017 ◽  
Vol 897 ◽  
pp. 115-118
Author(s):  
Martin Domeij ◽  
Jimmy Franchi ◽  
Krister Gumaelius ◽  
K. Lee ◽  
Fredrik Allerstam
Keyword(s):  
Threshold Voltage ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Subthreshold Slope ◽  
Gate Oxides ◽  
Channel Mobility

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.

Elevated Temperature Operation of 4H-SiC Nanoribbon Field Effect Transistors

2015 ◽  
Vol 15 (10) ◽  
pp. 7551-7554 ◽  
Author(s):  
Min Seok Kang ◽  
Susanna Yu ◽  
Sang Mo Koo
Keyword(s):  
Elevated Temperature ◽  
Plasma Etching ◽  
Field Effect ◽  
Heat Dissipation ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Top Down ◽  
Channel Mobility ◽  
Channel Thickness ◽  
Effective Channel

We fabricated 4H-SiC nanoribbon field effect transistors (FETs) of various channel thickness (tch) of 100∼500 nm by a “top–down” approach, using a lithography and plasma etching process. We studied the dependence of the device transfer characteristics on the channel geometry. This demonstrated that fabricated SiC nanoribbon FETs with a tch of 100 nm show normally-on characteristics, and have a threshold voltage of −12 V, and a maximum transconductance value of 8.8 mS, which shows improved drain current degradation of the SiC nanoribbon FETs with tch =100 nm at elevated temperature. This can be attributed to the improved heat dissipation, enhanced channel mobility, and together with widening of effective channel thickness depletion induced.

Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N2O Annealing

2006 ◽  
Vol 527-529 ◽  
pp. 987-990 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
H. Kawano ◽  
Masato Noborio ◽  
Jun Suda ◽  
Hiroyuki Matsunami
Keyword(s):  
Breakdown Strength ◽  
Oxide Thickness ◽  
Interface State ◽  
State Density ◽  
Interface Properties ◽  
Gate Oxides ◽  
Channel Mobility ◽  
Oxide Deposition ◽  
Mos Structures

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.

Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures

2008 ◽  
Vol 600-603 ◽  
pp. 679-682 ◽  
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Post Deposition Annealing ◽  
Interface Quality ◽  
Channel Mobility ◽  
Capacitance Voltage ◽  
Mis Capacitors ◽  
Post Deposition ◽  
Time Lead

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

Fabrication and Characterization of 4H-SiC MOSFET with MOCVD-Grown Al2O3 Gate Insulator

2007 ◽  
Vol 556-557 ◽  
pp. 787-790 ◽  
Author(s):  
Shiro Hino ◽  
Tomohiro Hatayama ◽  
Naruhisa Miura ◽  
Tatsuo Oomori ◽  
Eisuke Tokumitsu
Keyword(s):  
Photoelectron Spectroscopy ◽  
Chemical Vapor ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Organic Chemical ◽  
Mos Capacitors ◽  
Significant Difference ◽  
Metal Organic

We have fabricated and characterized MOS capacitors and lateral MOSFETs using Al2O3 as a gate insulator. Al2O3 films were deposited by metal-organic chemical vapor deposition (MOCVD) at temperatures as low as 190 oC using tri-ethyl-aluminum and H2O as precursors. We first demonstrate from the capacitance – voltage (C-V) measurements that the Al2O3/SiC interface has lower interface state density than the thermally-grown SiO2/SiC interface. No significant difference was observed between X-ray photoelectron spectroscopy (XPS) Si 2p spectrum from the Al2O3/SiC interface and that from the SiC substrate, which means the SiC substrate was not oxidized during the Al2O3 deposition. Next, we show that the fabricated lateral SiC-MOSFETs with Al2O3 gate insulator have good drain current – drain voltage (ID-VD) and drain current – gate voltage (ID-VG) characteristics with normally-off behavior. The obtained peak values of field-effect mobility (μFE) are between 68 and 88 cm2/Vs.

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