scholarly journals A random-walk benchmark for single-electron circuits

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
David Reifert ◽  
Martins Kokainis ◽  
Andris Ambainis ◽  
Vyacheslavs Kashcheyevs ◽  
Niels Ubbelohde
Keyword(s):  
Random Walk ◽  
Integrated Circuits ◽  
Quantum Systems ◽  
Quantum Circuits ◽  
Correlated Noise ◽  
Clock Frequency ◽  
Circuit Performance ◽  
Precise Control ◽  
Statistical Consistency ◽  
Fidelity Implementation

AbstractMesoscopic integrated circuits aim for precise control over elementary quantum systems. However, as fidelities improve, the increasingly rare errors and component crosstalk pose a challenge for validating error models and quantifying accuracy of circuit performance. Here we propose and implement a circuit-level benchmark that models fidelity as a random walk of an error syndrome, detected by an accumulating probe. Additionally, contributions of correlated noise, induced environmentally or by memory, are revealed as limits of achievable fidelity by statistical consistency analysis of the full distribution of error counts. Applying this methodology to a high-fidelity implementation of on-demand transfer of electrons in quantum dots we are able to utilize the high precision of charge counting to robustly estimate the error rate of the full circuit and its variability due to noise in the environment. As the clock frequency of the circuit is increased, the random walk reveals a memory effect. This benchmark contributes towards a rigorous metrology of quantum circuits.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

2007 ◽  
Vol 17 (2) ◽  
pp. 946-951 ◽  
Author(s):  
Sergey K. Tolpygo ◽  
D. Yohannes ◽  
R. T. Hunt ◽  
J. A. Vivalda ◽  
D. Donnelly ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Process Development ◽  
Clock Frequency

High Temperature Silicon Carbide CMOS Integrated Circuits

2011 ◽  
Vol 679-680 ◽  
pp. 726-729 ◽  
Author(s):  
David T. Clark ◽  
Ewan P. Ramsay ◽  
A.E. Murphy ◽  
Dave A. Smith ◽  
Robin. F. Thompson ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Band Gap ◽  
High Temperatures ◽  
Wide Band ◽  
Cmos Technology ◽  
Cmos Integrated Circuits ◽  
Wide Band Gap ◽  
Circuit Performance

The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.

Recent Developments in Mechanical Specimen Preparation for Tem and Sem Applications

1999 ◽  
Vol 5 (S2) ◽  
pp. 932-933
Author(s):  
W. Li ◽  
S. Q. Wang ◽  
R. Trussell ◽  
M. Xu ◽  
R.D. Venables ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Sample Preparation ◽  
Ion Beam ◽  
Wedge Angle ◽  
Specimen Preparation ◽  
Precise Control ◽  
Transmission Electron ◽  
Recent Developments ◽  
Polishing Tool

The continued reduction in the size of critical features in integrated circuits has resulted in the need to develop rapid, site-specific, sectioning techniques to enable efficient physical characterization of the structures of interest. We have implemented a mechanical polishing approach to achieve this objective with the additional goals of maximizing the number of targeted sites in a sample that can be analyzed, and minimizing physically destructive procedures, such as ion beam exposure. Precision sample preparation approaches have been under investigation for both transmission electron microscopy and scanning electron microscopy.The mechanical specimen preparation approach used in this work is a variant of the well-known wedge polishing technique. Here we use a polishing tool that does not contact the grinding surface, thus allowing precise control of the wedge angle. Prior to sample preparation, the polishing tool head was precision aligned parallel to the platen.

HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY

1995 ◽  
Vol 06 (01) ◽  
pp. 163-210 ◽  
Author(s):  
STEPHEN I. LONG
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Material Properties ◽  
High Speed ◽  
Digital Circuit ◽  
Bipolar Transistor ◽  
Clock Frequency ◽  
Digital Integrated Circuits ◽  
Heterojunction Devices ◽  
Circuit Technology

The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.

scholarly journals Advanced exact synthesis of Clifford+T circuits

2020 ◽  
Vol 19 (9) ◽  
Author(s):  
Philipp Niemann ◽  
Robert Wille ◽  
Rolf Drechsler
Keyword(s):  
Large Scale ◽  
Fault Tolerant ◽  
Logic Synthesis ◽  
Research Problem ◽  
Quantum Systems ◽  
Quantum Circuits ◽  
Research Attention ◽  
Small Quantum ◽  
Significant Research ◽  
Important Research Problem

Abstract Quantum systems provide a new way of conducting computations based on the so-called qubits. Due to the potential for significant speed-ups, this field received significant research attention in recent years. The Clifford+T library is a very promising and popular gate library for these kinds of computations. Unlike other libraries considered so far, it consists of only a small number of gates for all of which robust, fault-tolerant realizations are known for many technologies that seem to be promising for large-scale quantum computing. As a consequence, (logic) synthesis of Clifford+T quantum circuits became an important research problem. However, previous work in this area has several drawbacks: Corresponding approaches are either only applicable to very small quantum systems or lead to circuits that are far from being optimal. The latter is mainly caused by the fact that current synthesis realizes the desired circuit by a local, i.e., column-wise, consideration of the underlying unitary transformation matrix to be synthesized. In this paper, we analyze the conceptual drawbacks of this approach and propose to overcome them by taking a global view of the matrices and perform a separation of concerns regarding individual synthesis steps. We precisely describe a corresponding algorithm as well as its efficient implementation on top of decision diagrams. Experimental results confirm the resulting benefits and show improvements of up to several orders of magnitudes in costs compared to previous work.

scholarly journals Anomalous Stranski-Krastanov growth of (111)-oriented quantum dots with tunable wetting layer thickness

2019 ◽  
Vol 9 (1) ◽  
Author(s):  
Christopher F. Schuck ◽  
Simon K. Roy ◽  
Trent Garrett ◽  
Qing Yuan ◽  
Ying Wang ◽  
...  
Keyword(s):  
Quantum Dots ◽  
Self Assembly ◽  
Tensile Strain ◽  
Quantum Systems ◽  
Growth Mode ◽  
Wetting Layer ◽  
Precise Control ◽  
Growth Regime ◽  
Inp Substrates ◽  
Lattice Matched

AbstractDriven by tensile strain, GaAs quantum dots (QDs) self-assemble on In0.52Al0.48As(111)A surfaces lattice-matched to InP substrates. In this study, we show that the tensile-strained self-assembly process for these GaAs(111)A QDs unexpectedly deviates from the well-known Stranski-Krastanov (SK) growth mode. Traditionally, QDs formed via the SK growth mode form on top of a flat wetting layer (WL) whose thickness is fixed. The inability to tune WL thickness has inhibited researchers’ attempts to fully control QD-WL interactions in these hybrid 0D-2D quantum systems. In contrast, using microscopy, spectroscopy, and computational modeling, we demonstrate that for GaAs(111)A QDs, we can continually increase WL thickness with increasing GaAs deposition, even after the tensile-strained QDs (TSQDs) have begun to form. This anomalous SK behavior enables simultaneous tuning of both TSQD size and WL thickness. No such departure from the canonical SK growth regime has been reported previously. As such, we can now modify QD-WL interactions, with future benefits that include more precise control of TSQD band structure for infrared optoelectronics and quantum optics applications.

scholarly journals Hybrid quantum circuits: Superconducting circuits interacting with other quantum systems

2013 ◽  
Vol 85 (2) ◽  
pp. 623-653 ◽  
Author(s):  
Ze-Liang Xiang ◽  
Sahel Ashhab ◽  
J. Q. You ◽  
Franco Nori
Keyword(s):  
Quantum Systems ◽  
Quantum Circuits ◽  
Superconducting Circuits
Sign in / Sign up

Export Citation Format

Share Document