A Review on MOSFET-Like CNTFETs

2016 ◽  
Vol 4 (2) ◽  
pp. 124-129
Author(s):  
Vikash Prasad ◽  
◽  
Debaprasad Das
Keyword(s):  
Field Effect Transistor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Channel Length ◽  
Ring Oscillator ◽  
Design Decisions ◽  
Sram Cell ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Important Design

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.

scholarly journals Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

2019 ◽  
Vol 9 (6) ◽  
pp. 4933-4936
Author(s):  
H. Ghabri ◽  
D. Ben Issa ◽  
H. Samet
Keyword(s):  
Performance Optimization ◽  
Field Effect Transistor ◽  
Digital Circuits ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Signal Processors ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Signal Processors

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

scholarly journals Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

2021 ◽  
Author(s):  
Md Azmot Ullah Khan ◽  
Naheem Olakunle Adesina ◽  
Jian Xu
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Ring Oscillator ◽  
Limiting Factor ◽  
Vlsi Circuit ◽  
Half Adder ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Output Characteristics ◽  
Power Delay Product

Abstract This paper presents the design of an inverter, half adder, and ring oscillator using compact models of MoS2 channel-based tunnel field effect transistor (TFET). The TFET models (both n and p-type) are written in high-level hardware language Verilog-Analog (Verilog-A) following the analytical model of [1] and the output characteristics of the components are simulated in Cadence/Spectre software. The performance of the designed inverter (a basic building block of VLSI circuit) is analyzed by extracting its different parameters, such as transfer characteristics, power dissipation and consumption, delay, power delay product. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Moreover, our observation reveals that the ring oscillator can operate at a higher frequency with lower power consumption in comparison to the existing CMOS and GFET technologies. We have also reported an improvement to the limiting factor of ring oscillator performance i.e. phase noise at two different offset frequencies. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low-power VLSI circuit.

High Stable and Low Power 8T CNTFET SRAM Cell

2019 ◽  
Vol 29 (05) ◽  
pp. 2050080
Author(s):  
M. Elangovan ◽  
K. Gunavathi
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Sram Cell ◽  
Effect Transistor

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

Patterning rubrene crystalline thin films for sub-micrometer channel length field-effect transistor arrays

2014 ◽  
Vol 2 (44) ◽  
pp. 9359-9363 ◽  
Author(s):  
Juan Zhu ◽  
Wenchong Wang ◽  
Qigang Zhong ◽  
Liqiang Li ◽  
Chuan Du ◽  
...  
Keyword(s):  
Thin Films ◽  
Field Effect ◽  
Carrier Mobility ◽  
Field Effect Transistor ◽  
Channel Length ◽  
Organic Films ◽  
Porous Structures ◽  
Patterned Growth ◽  
Effect Transistor ◽  
Magnitude Difference

The patterned growth of crystalline rubrene films directly on electrodes is demonstrated. In addition, organic films with close packed and porous structures are locally achieved by controlling the electrode spaces, resulting in a two orders of magnitude difference in carrier mobility.

scholarly journals Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci
Keyword(s):  
High Frequency ◽  
Communication Systems ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Geometrical Parameters ◽  
Effect Transistor ◽  
Rf Performance ◽  
The Impact

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

A metal‐oxide‐semiconductor field‐effect transistor with a 20‐nm channel length

1990 ◽  
Vol 68 (5) ◽  
pp. 2493-2495 ◽  
Author(s):  
A. Hartstein ◽  
N. F. Albert ◽  
A. A. Bright ◽  
S. B. Kaplan ◽  
B. Robinson ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Channel Length ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Transistor ◽  
20 Nm

Design of ternary subtractor using multiplexers

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tulasi Naga Jyothi Kolanti ◽  
Vasundhara Patel K.S.
Keyword(s):  
Field Effect Transistors ◽  
Process Variations ◽  
Propagation Delay ◽  
Channel Length ◽  
Binary Decision ◽  
Content Type ◽  
The Stability ◽  
Power Delay Product ◽  
Ternary Decision Diagram ◽  
Logic Functions

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

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