scholarly journals 0.6 V, 116 nW Neural Spike Acquisition IC with Self-Biased Instrumentation Amplifier and Analog Spike Extraction

Sensors ◽  
2018 ◽  
Vol 18 (8) ◽  
pp. 2460 ◽  
Author(s):  
Jong Kim ◽  
Hankyu Lee ◽  
Hyoungho Ko
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Energy Operator ◽  
Open Loop ◽  
Instrumentation Amplifier ◽  
Neural Spike ◽  
Self Bias ◽  
Ultralow Power ◽  
Ia Current

This paper presents an ultralow power 0.6 V 116 nW neural spike acquisition integrated circuit with analog spike extraction. To reduce power consumption, an ultralow power self-biased current-balanced instrumentation amplifier (IA) is proposed. The passive RC lowpass filter in the amplifier acts as both DC servo loop and self-bias circuit. The spike detector, based on an analog nonlinear energy operator consisting of a low-voltage open-loop differentiator and an open-loop gate-bulk input multiplier, is designed to emphasize the high frequency spike components nonlinearly. To reduce the spike detection error, the adjacent spike merger is also proposed. The proposed circuit achieves a low IA current consumption of 46.4 nA at 0.6 V, noise efficiency factor (NEF) of 1.81, the bandwidth from 102 Hz to 1.94 kHz, the input referred noise of 9.37 μVrms, and overall power consumption of 116 nW at 0.6 V. The proposed circuit can be used in the ultralow power spike pulses acquisition applications, including the neurofeedback systems on peripheral nerves with low neuron density.

scholarly journals Low-power ASIC suitable for miniaturized wireless EMG systems

2019 ◽  
Vol 70 (5) ◽  
pp. 393-399 ◽  
Author(s):  
Vilem Kledrowetz ◽  
Roman Prokop ◽  
Lukas Fujcik ◽  
Michal Pavlik ◽  
Jiří Háze
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Low Voltage ◽  
Cmos Technology ◽  
Instrumentation Amplifier ◽  
Pass Filter ◽  
Delta Sigma ◽  
Pulse Density ◽  
Wide Range

Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

POWER SAVING CIRCUIT DESIGN TECHNIQUES FOR IMPLANTABLE NEURO-STIMULATORS

2012 ◽  
Vol 21 (06) ◽  
pp. 1240016 ◽  
Author(s):  
TORSTEN LEHMANN ◽  
HOSUNG CHUN ◽  
YUANYUAN YANG
Keyword(s):  
Power Consumption ◽  
Circuit Design ◽  
Power Supply ◽  
Integrated Circuit ◽  
Power Efficiency ◽  
Low Voltage ◽  
Power Saving ◽  
Design Approach ◽  
Electrode Impedance ◽  
Design Techniques

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved.

Comparison of Dc-Dc SEPIC, CUK and Flyback Converters Based LED Drivers

2020 ◽  
pp. 99-107
Author(s):  
Erdal Sehirli
Keyword(s):  
Integrated Circuit ◽  
Closed Loop ◽  
Input Voltage ◽  
Open Loop ◽  
Current Sensor ◽  
Switching Frequency ◽  
Led Driver ◽  
Advantages And Disadvantages ◽  
Led Drivers ◽  
Conduction Mode

This paper presents the comparison of LED driver topologies that include SEPIC, CUK and FLYBACK DC-DC converters. Both topologies are designed for 8W power and operated in discontinuous conduction mode (DCM) with 88 kHz switching frequency. Furthermore, inductors of SEPIC and CUK converters are wounded as coupled. Applications are realized by using SG3524 integrated circuit for open loop and PIC16F877 microcontroller for closed loop. Besides, ACS712 current sensor used to limit maximum LED current for closed loop applications. Finally, SEPIC, CUK and FLYBACK DC-DC LED drivers are compared with respect to LED current, LED voltage, input voltage and current. Also, advantages and disadvantages of all topologies are concluded.

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

2018 ◽  
Vol 6 (8) ◽  
pp. 53
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Low Voltage ◽  
Performance Comparison ◽  
Low Noise ◽  
Center Frequency ◽  
Voltage Controlled Oscillator ◽  
Low Phase Noise ◽  
Lc Vco

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Simultaneous Voltage and Current Measurement Instrumentation Amplifier for ECG and PPG Monitoring

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 679
Author(s):  
Jongpal Kim
Keyword(s):  
Integrated Circuit ◽  
Cardiovascular Health ◽  
Current Noise ◽  
Instrumentation Amplifier ◽  
Current Sensing ◽  
Application Specific Integrated Circuit ◽  
Time Division ◽  
Electrocardiogram Ecg ◽  
First Time ◽  
Application Specific

An instrumentation amplifier (IA) capable of sensing both voltage and current at the same time has been introduced and applied to electrocardiogram (ECG) and photoplethysmogram (PPG) measurements for cardiovascular health monitoring applications. The proposed IA can switch between the voltage and current sensing configurations in a time–division manner faster than the ECG and PPG bandwidths. The application-specific integrated circuit (ASIC) of the proposed circuit design was implemented using 180 nm CMOS fabrication technology. Input-referred voltage noise and current noise were measured as 3.9 µVrms and 172 pArms, respectively, and power consumption was measured as 34.9 µA. In the current sensing configuration, a current noise reduction technique is applied, which was confirmed to be a 25 times improvement over the previous version. Using a single IA, ECG and PPG can be monitored in the form of separated ECG and PPG signals. In addition, for the first time, a merged ECG/PPG signal is acquired, which has features of both ECG and PPG peaks.

Multi-level phase-change memory with ultralow power consumption and resistance drift

2021 ◽  
Author(s):  
Bin Liu ◽  
Kaiqi Li ◽  
Wanliang Liu ◽  
Jian Zhou ◽  
Liangcai Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Phase Change ◽  
Phase Change Memory ◽  
Multi Level ◽  
Ultralow Power ◽  
Change Memory

A High Step-up DC-DC Converter Based on the Voltage Lift Technique for Renewable Energy Applications

2021 ◽  
Vol 13 (19) ◽  
pp. 11059
Author(s):  
Shahrukh Khan ◽  
Arshad Mahmood ◽  
Mohammad Zaid ◽  
Mohd Tariq ◽  
Chang-Hua Lin ◽  
...  
Keyword(s):  
Renewable Energy ◽  
Common Ground ◽  
Closed Loop ◽  
Low Voltage ◽  
Renewable Energy Sources ◽  
Input Voltage ◽  
High Gain ◽  
Boost Converter ◽  
Open Loop ◽  
Voltage Gain

High gain DC-DC converters are getting popular due to the increased use of renewable energy sources (RESs). Common ground between the input and output, low voltage stress across power switches and high voltage gain at lower duty ratios are desirable features required in any high gain DC-DC converter. DC-DC converters are widely used in DC microgrids to supply power to meet local demands. In this work, a high step-up DC-DC converter is proposed based on the voltage lift (VL) technique using a single power switch. The proposed converter has a voltage gain greater than a traditional boost converter (TBC) and Traditional quadratic boost converter (TQBC). The effect of inductor parasitic resistances on the voltage gain of the converter is discussed. The losses occurring in various components are calculated using PLECS software. To confirm the performance of the converter, a hardware prototype of 200 W is developed in the laboratory. The simulation and hardware results are presented to determine the performance of the converter in both open-loop and closed-loop conditions. In closed-loop operation, a PI controller is used to maintain a constant output voltage when the load or input voltage is changed.

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