scholarly journals Enhancing AlN PMUTs’ Acoustic Responsivity within a MEMS-on-CMOS Process

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8447
Author(s):  
Eyglis Ledesma ◽  
Ivan Zamora ◽  
Arantxa Uranga ◽  
Francesc Torres ◽  
Núria Barniol
Keyword(s):  
Residual Stress ◽  
Acoustic Pressure ◽  
Cmos Technology ◽  
Coupling Factor ◽  
Passive Layer ◽  
Thin Layers ◽  
Cmos Process ◽  
Ultrasound Transducers ◽  
Monolithically Integrated ◽  
Acoustic Characterization

In this paper, guidelines for the optimization of piezoelectrical micromachined ultrasound transducers (PMUTs) monolithically integrated over a CMOS technology are developed. Higher acoustic pressure is produced by PMUTs with a thin layer of AlN piezoelectrical material and Si3N4 as a passive layer, as is studied here with finite element modeling (FEM) simulations and experimental characterization. Due to the thin layers used, parameters such as residual stress become relevant as they produce a buckled structure. It has been reported that the buckling of the membrane due to residual stress, in general, reduces the coupling factor and consequently degrades the efficiency of the acoustic pressure production. In this paper, we show that this buckling can be beneficial and that the fabricated PMUTs exhibit enhanced performance depending on the placement of the electrodes. This behavior was demonstrated experimentally and through FEM. The acoustic characterization of the fabricated PMUTs shows the enhancement of the PMUT performance as a transmitter (with 5 kPa V−1 surface pressure for a single PMUT) and as a receiver (12.5 V MPa−1) in comparison with previously reported devices using the same MEMS-on-CMOS technology as well as state-of-the-art devices.

scholarly journals A Tunable-Gain Transimpedance Amplifier for CMOS-MEMS Resonators Characterization

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 82
Author(s):  
Rafel Perelló-Roig ◽  
Jaume Verd ◽  
Sebastià Bota ◽  
Jaume Segura
Keyword(s):  
Cmos Technology ◽  
Open Loop ◽  
Transimpedance Amplifier ◽  
Mems Devices ◽  
Monolithically Integrated ◽  
Mems Resonators ◽  
Electromechanical Performance ◽  
Cmos Mems ◽  
Promising Solution ◽  
On Chip

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This paper presents a transimpedance amplifier (TIA) fabricated using a commercial 0.35-µm CMOS technology specifically oriented to drive and sense monolithically integrated CMOS-MEMS resonators up to 50 MHz with a tunable transimpedance gain ranging from 112 dB to 121 dB. The output voltage noise is as low as 225 nV/Hz1/2—input-referred current noise of 192 fA/Hz1/2—at 10 MHz, and the power consumption is kept below 1-mW. In addition, the TIA amplifier exhibits an open-loop gain independent of the parasitic input capacitance—mostly associated with the MEMS layout—representing an advantage in MEMS testing compared to other alternatives such as Pierce oscillator schemes. The work presented includes the characterization of three types of MEMS resonators that have been fabricated and experimentally characterized both in open-loop and self-sustained configurations using the integrated TIA amplifier. The experimental characterization includes an accurate extraction of the electromechanical parameters for the three fabricated structures that enables an accurate MEMS-CMOS circuitry co-design.

scholarly journals Simple and Versatile Analytical Method for Monitoring the Deposition of Thin Layers by Optical Measurement and Calculation of Residual Stress

2021 ◽  
Vol 725 ◽  
pp. 138635
Author(s):  
Quentin Hatte ◽  
Mireille Richard-Plouet ◽  
Pierre-Yves Jouan ◽  
Pascal Casari ◽  
Pierre-Antoine Dubos
Keyword(s):  
Residual Stress ◽  
Analytical Method ◽  
Optical Measurement ◽  
Thin Layers

Extensive Experimental Study on Diaphragm-Based Piezoelectric Microphone

1999 ◽  
Author(s):  
Meng-Nian Niu ◽  
Hong Zeng ◽  
Hai Yan ◽  
Eun Sok Kim
Keyword(s):  
Residual Stress ◽  
Experimental Study ◽  
Acoustic Pressure ◽  
Structural Integrity ◽  
Vertical Displacement ◽  
Active Area ◽  
Zno Film ◽  
Beam Laser ◽  
Acoustic Chamber ◽  
Focused Beam

Abstract This paper reports our extensive experimental study on diaphragm-based piezoelectric microphones fabricated on a silicon substrate. We have fabricated and carefully analyzed about 60 micromachined piezoelectric microphones (composed of piezoelectric ZnO film, insulating layers and electrodes) built on a low-stress silicon nitride diaphragm (with and without corrugation on the diaphragm and with five kinds of residual stress in the diaphragm). Microphone sensitivity is measured in an acoustic chamber with a B&K4135 microphone. Vertical displacement of a microphone diaphragm under an applied acoustic pressure is measured with a focused-beam laser Doppler displacement meter. Our results show that (1) corrugation releases both tensile stress and compressive stress effectively, and increases the center displacement greatly, (2) a good bending curvature in the active area is needed for a good microphone sensitivity, and (3) ZnO structural integrity is the major factor that affects the bending curvature in the active area.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

scholarly journals Fabrication of a CMOS-based Imaging Chip with Monolithically Integrated RGB and NIR Filters

Proceedings ◽  
2019 ◽  
Vol 2 (13) ◽  
pp. 751
Author(s):  
Bart Vereecke ◽  
Els Van Besien ◽  
Deniz Sabuncuoglu Tezcan ◽  
Nick Spooren ◽  
Nicolaas Tack ◽  
...  
Keyword(s):  
Bandpass Filter ◽  
Imaging System ◽  
Low Cost ◽  
Cmos Technology ◽  
Image Sensors ◽  
Single Chip ◽  
Interference Filters ◽  
Monolithically Integrated ◽  
Recent Developments

Recent developments in multispectral cameras have demonstrated how compact and low-cost spectral sensors can be made by monolithically integrating filters on top of commercially available image sensors. In this paper, the fabrication of a RGB + NIR variation to such a single-chip imaging system is described, including the integration of a metallic shield to minimize crosstalk, and two interference filters: a NIR blocking filter, and a NIR bandpass filter. This is then combined with standard polymer based RGB colour filters. Fabrication of this chip is done in imec’s 200 mm cleanroom using standard CMOS technology, except for the addition of RGB colour filters and microlenses, which is outsourced.

scholarly journals Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 436 ◽  
Author(s):  
Chin-An Hsieh ◽  
Chia-Ming Tsai ◽  
Bing-Yue Tsui ◽  
Bo-Jen Hsiao ◽  
Sheng-Di Lin
Keyword(s):  
Detection Probability ◽  
Single Photon ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Single Photons ◽  
Photon Detection ◽  
Important Indicator ◽  
Avalanche Diodes ◽  
Single Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication.

scholarly journals A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2198
Author(s):  
Zhichao Li ◽  
Shiheng Yang ◽  
Samuel B. S. Lee ◽  
Kiat Seng Yeo
Keyword(s):  
Output Power ◽  
Effective Conductivity ◽  
Building Blocks ◽  
Cmos Technology ◽  
Center Frequency ◽  
Cmos Process ◽  
Two Stage ◽  
Power Added Efficiency ◽  
X Band ◽  
Compact Size

For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

scholarly journals Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4663
Author(s):  
Rafel Perello-Roig ◽  
Jaume Verd ◽  
Sebastià Bota ◽  
Jaume Segura
Keyword(s):  
Fluid Flow ◽  
Gas Sensing ◽  
Low Cost ◽  
Cmos Technology ◽  
Monolithically Integrated ◽  
Impact Reduction ◽  
Mems Resonators ◽  
Cmos Mems ◽  
Outstanding Result ◽  
The Impact

Based on experimental data, this paper thoroughly investigates the impact of a gas fluid flow on the behavior of a MEMS resonator specifically oriented to gas sensing. It is demonstrated that the gas stream action itself modifies the device resonance frequency in a way that depends on the resonator clamp shape with a corresponding non-negligible impact on the gravimetric sensor resolution. Results indicate that such an effect must be accounted when designing MEMS resonators with potential applications in the detection of volatile organic compounds (VOCs). In addition, the impact of thermal perturbations was also investigated. Two types of four-anchored CMOS-MEMS plate resonators were designed and fabricated: one with straight anchors, while the other was sustained through folded flexure clamps. The mechanical structures were monolithically integrated together with an embedded readout amplifier to operate as a self-sustained fully integrated oscillator on a commercial CMOS technology, featuring low-cost batch production and easy integration. The folded flexure anchor resonator provided a flow impact reduction of 5× compared to the straight anchor resonator, while the temperature sensitivity was enhanced to −115 ppm/°C, an outstanding result compared to the −2403 ppm/°C measured for the straight anchored structure.

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