The method of parallel-sequential built-in self-testing in integrated circuits of the type SFPGAS

2007 ◽  
Vol 68 (1) ◽  
pp. 149-159 ◽  
Author(s):  
G. P. Aksenova ◽  
V. F. Khalchev
Keyword(s):  
Integrated Circuits ◽  
Self Testing

scholarly journals Design for Testability of Integrated Circuits and Project Protection Difficulties

2019 ◽  
Vol 7 (4) ◽  
pp. 60-70
Author(s):  
E. Ph. Pevtsov ◽  
T. A. Demenkova ◽  
A. A. Shnyakin
Keyword(s):  
Integrated Circuits ◽  
Design For Testability ◽  
Design Stage ◽  
Malicious Nodes ◽  
Full Disclosure ◽  
Testing Procedures ◽  
Foreign Companies ◽  
Current Consumption ◽  
Self Testing ◽  
Foreign Supplier

Design solutions of domestic VLSI were obtained as a result of the application of computeraided design tools of a foreign supplier (CAD Synopsys, Cadence Design Systems and Mentor Graphics), based on standard libraries of PDK elements (Project Design KIT) of factories and IC-modules also supplied mainly by foreign companies. As a rule, the developer does not have its own production facilities, using the services provided by foreign factories (fablesscompanies). Due to this fact, relevant are the studies aimed at the development of a complex of measures, excluding the possibility of unauthorized changes into IC, i.e. protection of projects against intentional hardware and technology violations made during the formation of the control information for handing it over to the production facility and/or in case of IC manufacture at the factory. This paper considers this task from the standpoint of the analysis of the methodology of design for testability (DFT), i.e., a complex of measures that provide obtaining solutions at the design stage. The solutions include the verification of the correct performance of the manufactured chip by means of external tests and/or self-testing procedures. It was proposed, inter alia: 1) to analyze the libraries of standard elements used in the project with full disclosure of their specifications; 2) to create nodes with the physical non-cloning function in the projects on the basis of the libraries of standard elements in models and analysis programs; 3) to analyze IP modules used in the project with the maximum disclosure of structure, methods and algorithms for providing test coverings; 4) to provide for the development in projects of special test kits and methods of their generation at the design stage of functions in order to detect malicious nodes and programs both within SoC cores and at the level of system buses; 5) to develop at the design stage and to apply during tests a technique of special hardware measurements of parameters of the manufactured circuits and analysis of their results, inter alia, according to measurements of delays in distribution of signals and/or buses current consumption.

Low-level logic fault testing ASIC simulation environment

2014 ◽  
Vol 11 (3) ◽  
pp. 279-286 ◽  
Author(s):  
Mansour Assaf ◽  
Leslie-Ann Moore ◽  
Sunil Das ◽  
Satyendra Biswas ◽  
Scott Morton
Keyword(s):  
Integrated Circuits ◽  
Test Pattern ◽  
Simulation Environment ◽  
Fault Testing ◽  
Low Level ◽  
Self Testing ◽  
Ip Cores ◽  
Application Specific ◽  
Test Architecture ◽  
Total Test

A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA

2008 ◽  
Vol 144 ◽  
pp. 214-219
Author(s):  
Vidas Abraitis ◽  
Žydrūnas Tamoševičius
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Test Pattern ◽  
Pattern Generation ◽  
Linear Feedback ◽  
Test Sequence ◽  
Self Testing ◽  
Field Programmable ◽  
Application Specific Integrated Circuit ◽  
Transition Delay

Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

The study of interfacial reactions of nickel thin films on GaAs

1983 ◽  
Vol 41 ◽  
pp. 156-157
Author(s):  
L.J. Chen ◽  
Y.F. Hsieh
Keyword(s):  
Thin Films ◽  
Integrated Circuits ◽  
Interfacial Reactions ◽  
Metal Contacts ◽  
Nickel Thin Films ◽  
Thin Foils ◽  
The Status ◽  
Si Doped ◽  
Electron Microscopes

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Failure Analysis With the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 482-483
Author(s):  
John R. Devaney
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
High Reliability ◽  
Military Applications ◽  
Small Structure ◽  
Useful Life ◽  
Insight Into ◽  
Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

Stress Relaxation and the Formation of Silicides in the Process of the Crystallization of NI-NB Films on SI

1991 ◽  
Vol 49 ◽  
pp. 898-899
Author(s):  
N. Rozhanski ◽  
V. Lifshitz
Keyword(s):  
Thin Films ◽  
Stress Relaxation ◽  
Integrated Circuits ◽  
Direct Evidence ◽  
Alloy Film ◽  
Diffusion Barriers ◽  
Effective Barrier

Thin films of amorphous Ni-Nb alloys are of interest since they can be used as diffusion barriers for integrated circuits on Si. A native SiO2 layer is an effective barrier for Ni diffusion but it deformation during the crystallization of the alloy film lead to the appearence of diffusion fluxes through it and the following formation of silicides. This study concerns the direct evidence of the action of stresses in the process of the crystallization of Ni-Nb films on Si and the structure of forming NiSi2 islands.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Analytical electron microscopy of grain boundaries in Al-Cu metallizations

1992 ◽  
Vol 50 (2) ◽  
pp. 1684-1685
Author(s):  
J. R. Michael ◽  
A. D. Romig ◽  
D. R. Frear
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Failure Mode ◽  
Current Density ◽  
Thermal History ◽  
Analytical Electron Microscopy ◽  
Cu Metallization ◽  
Analytical Electron ◽  
Interconnect Lines

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits, the Cu being added since it improves resistance to electromigration failure. As linewidths decrease to submicrometer dimensions, the current density carried by the interconnect increases dramatically and the probability of electromigration failure increases. To increase the robustness of the interconnect lines to this failure mode, an understanding of the mechanism by which Cu improves resistance to electromigration is needed. A number of theories have been proposed to account for role of Cu on electromigration behavior and many of the theories are dependent of the elemental Cu distribution in the interconnect line. However, there is an incomplete understanding of the distribution of Cu within the Al interconnect as a function of thermal history. In order to understand the role of Cu in reducing electromigration failures better, it is important to characterize the Cu distribution within the microstructure of the Al-Cu metallization.

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