Understanding and Controlling Cu Protrusions in 3D TSV Processing

Cu-filled through-silicon vias (TSVs) are an essential building block of 3D and 2.5D integrated chips. In the TSV-mid processing flow, which has emerged as an industry mainstream, one or more on-chip wiring levels are formed after the TSV Cu fill is completed, which exposes the fill to peak temperatures of up to 400 °C. Due to the higher coefficient of thermal expansion (CTE) of Cu than the surrounding silicon and dielectrics, the TSV fill protrudes above the level previously defined by the TSV chemical mechanical polishing (CMP) step. Even after returning to room temperature, the top of the TSV will not occupy the same space due to plastic deformation during the thermal treatment. This phenomenon is known as Cu protrusions, pumping, or popping. Excessive amounts of Cu protrusion present a risk to yields and reliability because the expansion can damage dielectrics and wiring above or adjacent to the TSVs. In this study, we report the underlying mechanisms as well as process remedies for Cu protrusions. The SEMATECH 5 um × 50 um TSV process and learning vehicle is used to conduct process split experiments comparing various plating chemistries, plating recipes, and post-plating anneal conditions. Stresses in the surrounding silicon are studied by micro-Raman, and a distinct signature distinguishing good from bad Cu protrusion behavior is identified. Cu material properties such as contamination, grain size, grain orientation, and strain may also influence the protrusion behavior; these factors are studied by micro-secondary ion mass spectroscopy (SIMS) and electron backscatter spectroscopy (EBSD). Our results shows that the choice of plating chemistry and subsequent optimized post-plating anneal are the main factors in suppressing Cu protrusions. Our best known method is able to reduce Cu protrusions to about 15 nm after typical thermal loads.