CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER

2009 ◽  
Vol 18 (01) ◽  
pp. 199-208 ◽  
Author(s):  
JEONG BEOM KIM
Keyword(s):  
Supply Voltage ◽  
Current Mode ◽  
Full Adder ◽  
Cmos Technology ◽  
Cmos Circuits ◽  
Cmos Circuit ◽  
Circuit Performance ◽  
Quaternary Logic ◽  
Binary Logic ◽  
Multiple Valued Logic

This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm standard CMOS technology with the supply voltage 2.5 V.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

scholarly journals Design and implementation of 4 bit binary weighted current steering DAC

2020 ◽  
Vol 10 (6) ◽  
pp. 5642
Author(s):  
Jayeshkumar J. Patel ◽  
Amisha P. Naik
Keyword(s):  
Supply Voltage ◽  
Biomedical Application ◽  
Current Mode ◽  
Cmos Technology ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Transmission Gate ◽  
Linearity Error ◽  
Current Steering Dac ◽  
Binary Weighted

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

scholarly journals Low-Power High-Speed Double Gate 1-bit Full Adder Cell

2016 ◽  
Vol 62 (4) ◽  
pp. 329-334 ◽  
Author(s):  
Raushan Kumar ◽  
Sahadev Roy ◽  
C.T. Bhunia
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Pass Transistor ◽  
Voltage Swing

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

scholarly journals Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Shikha Panwar ◽  
Mayuresh Piske ◽  
Aatreya Vivek Madgula
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Circuits ◽  
Output Node ◽  
Critical Sections

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

scholarly journals 1.5-V CMOS Current Multiplier/Divider

2018 ◽  
Vol 8 (3) ◽  
pp. 1478 ◽  
Author(s):  
Jetsdaporn Satansup ◽  
Worapong Tangsrirat
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Total Power ◽  
Total Power Consumption ◽  
Linearity Error ◽  
Low Supply Voltage ◽  
Circuit Technique

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented.  It is based on the use of a compact current quadratic cell able to operate at low supply voltage.  The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V.  Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.

scholarly journals Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder

2021 ◽  
Vol 5 (1) ◽  
pp. 1-7
Author(s):  
S. MOHAN DAS ◽  
GANESH KUMAR M ◽  
BHASKARA RAO K
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Universal Logic ◽  
Significant Saving ◽  
Low Leakage ◽  
Low Threshold ◽  
The Cost

This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.

An Energy Efficient Logic Approach to Implement CMOS Full Adder

2017 ◽  
Vol 26 (05) ◽  
pp. 1750084 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Supply Voltage ◽  
Signal Integrity ◽  
Full Adder ◽  
Cmos Technology ◽  
Nand Gate ◽  
Common Environment ◽  
Logic Approach ◽  
Power Delay Product

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90[Formula: see text]nm technology operating at 1.2[Formula: see text]V supply voltage and UMC 55[Formula: see text]nm CMOS technology operating at 1.0[Formula: see text]V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

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