Voltage controlled delay line for digital signal

This paper describes dual delay locked loop architecture with a mixed mode phase tuning method. The circuit accomplishes low jitter, unlimited phase shift in a large operating range, and accurate phase alignment with high resolution for relatively low input clock frequency. The architecture employs two DLL loops. The first one is digital and is used for generating coarsely spaced clock pulses, while the second is analog and is intended for accurate and precise fine phase shifting. Simulations show that this circuit has 2?r radians phase shift capability, and can resolve 25ps phase error at input clock frequency of 1MHz, using 1.2^m double-metal double-poly CMOS technology.

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AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

Journal of Circuits System and Computers ◽

10.1142/s0218126612400257 ◽

2012 ◽

Vol 21 (08) ◽

pp. 1240025 ◽

Cited By ~ 1

Author(s):

CHUN-YUAN CHENG ◽

JINN-SHYAN WANG ◽

CHENG-TAI YEH

Keyword(s):

Low Power ◽

Power Dissipation ◽

Low Voltage ◽

Cmos Technology ◽

Maximum Frequency ◽

Clock Frequency ◽

Power Efficient ◽

Delay Locked Loop ◽

Measurement Results ◽

Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

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A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

Sensors ◽

10.3390/s22010284 ◽

2021 ◽

Vol 22 (1) ◽

pp. 284

Author(s):

Jiyun Tong ◽

Sha Wang ◽

Shuang Zhang ◽

Mengdi Zhang ◽

Ye Zhao ◽

...

Keyword(s):

Closed Loop ◽

Delay Line ◽

Search Algorithm ◽

Cmos Technology ◽

Binary Search ◽

Delay Lines ◽

Delay Locked Loop ◽

Binary Search Algorithm ◽

Pvt Variations ◽

Low Jitter

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

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Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078721000088 ◽

2021 ◽

pp. 1-9

Author(s):

Philipp Ritter

Keyword(s):

Millimeter Wave ◽

Flip Chip ◽

Printed Circuit Board ◽

Digital Signal ◽

Cmos Technology ◽

Radar System ◽

Circuit Board ◽

Processing Unit ◽

Automotive Radar ◽

On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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Design of Multi Standard Near Field Communication Outphasing Transmitter with Modulation Wave Shaping

Electronics ◽

10.3390/electronics10020188 ◽

2021 ◽

Vol 10 (2) ◽

pp. 188

Author(s):

Žiga Korošak ◽

Nejc Suhadolnik ◽

Anton Pleteršek

Keyword(s):

Radio Frequency Identification ◽

High Efficiency ◽

Near Field ◽

Cmos Technology ◽

Near Field Communication ◽

Differential Delay ◽

Fully Differential ◽

Delay Locked Loop ◽

Modulation Wave ◽

The Individual

The aim of this work is to tackle the problem of modulation wave shaping in the field of near field communication (NFC) radio frequency identification (RFID). For this purpose, a high-efficiency transmitter circuit was developed to comply with the strict requirements of the newest EMVCo and NFC Forum specifications for pulse shapes. The proposed circuit uses an outphasing modulator that is based on a digital-to-time converter (DTC). The DTC based outphasing modulator supports amplitude shift keying (ASK) modulation, operates at four times the 13.56 MHz carrier frequency and is made fully differential in order to remove the parasitic phase modulation components. The accompanying transmitter logic includes lookup tables with programmable modulation pulse wave shapes. The modulator solution uses a 64-cell tapped current controlled fully differential delay locked loop (DLL), which produces a 360° delay at 54.24 MHz, and a glitch-free multiplexor to select the individual taps. The outphased output from the modulator is mixed to create an RF pulse width modulated (PWM) output, which drives the antenna. Additionally, this implementation is fully compatible with D-class amplifiers enabling high efficiency. A test circuit of the proposed differential multi-standard reader’s transmitter was simulated in 40 nm CMOS technology. Stricter pulse shape requirements were easily satisfied, while achieving an output linearity of 0.2 bits and maximum power consumption under 7.5 mW.

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The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences ◽

10.3390/app11010429 ◽

2021 ◽

Vol 11 (1) ◽

pp. 429

Author(s):

Min-Su Kim ◽

Youngoo Yang ◽

Hyungmo Koo ◽

Hansik Oh

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Low Power ◽

High Speed ◽

Cmos Technology ◽

Clock Frequency ◽

Clock Generation ◽

Allocation Method ◽

Evaluation Board ◽

28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽

10.3390/electronics10020177 ◽

2021 ◽

Vol 10 (2) ◽

pp. 177

Author(s):

Dongjun Park ◽

Sungwook Choi ◽

Jongsun Kim

Keyword(s):

Sampling Technique ◽

Cmos Process ◽

Detection Range ◽

Delay Locked Loop ◽

Delta Sigma Modulator ◽

Correlated Double Sampling ◽

Delta Sigma ◽

Fast Power ◽

Low Jitter ◽

Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

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Static Switching Dynamic Buffer Circuit

Journal of Engineering ◽

10.1155/2013/646214 ◽

2013 ◽

Vol 2013 ◽

pp. 1-11

Author(s):

A. K. Pandey ◽

R. A. Mishra ◽

R. K. Nagaria

Keyword(s):

Power Consumption ◽

Power Supply ◽

Loading Condition ◽

Cmos Technology ◽

Clock Frequency ◽

Logic Function ◽

Output Node ◽

Switching Dynamic ◽

Power Delay Product ◽

Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

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A 60 GHz reconfigurable active phase shifter based on a vector modulator in 65 nm CMOS technology

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078716000167 ◽

2016 ◽

Vol 8 (3) ◽

pp. 399-404 ◽

Cited By ~ 1

Author(s):

Boris Moret ◽

Nathalie Deltimple ◽

Eric Kerhervé ◽

Baudouin Martineau ◽

Didier Belot

Keyword(s):

Phase Shift ◽

Phase Shifter ◽

Complementary Metal Oxide Semiconductor ◽

Active Phase ◽

Cmos Technology ◽

Oxide Semiconductor ◽

60 Ghz ◽

Semiconductor Technology ◽

Vector Modulator ◽

Active Phase Shifter

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.

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