scholarly journals A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

2011 ◽  
Vol 9 ◽  
pp. 247-253 ◽  
Author(s):  
T. Heselhaus ◽  
T. G. Noll
Keyword(s):  
Threshold Voltage ◽  
Power Reduction ◽  
Access Time ◽  
Memory Cells ◽  
Charge Voltage ◽  
Voltage Level ◽  
Noise Margin ◽  
Sram Cell ◽  
Ground Line ◽  
Line Noise

Abstract. The conventional sensing scheme of single-ended read-only-ports as integrated in 8T-SRAM cells suffers from low performance compared to double-ended complementary sensing schemes. In the proposed sensing scheme the pre-charge voltage of the single-ended read-bit-line is set to a level above the threshold voltage of the sensing device with an adjustable margin. This margin is minimized to speed up the read access on the one hand and kept large enough to provide a sufficient bit-line noise margin on the other hand. The pre-charge voltage level of the proposed sensing circuit tracks the threshold voltage of the sensing device under process variations in order to maintain a minimum required bit-line noise margin. To avoid unnecessary bit-line discharging, the proposed sensing scheme employs a modified 8T-SRAM cell. Compared to the conventional 8T-SRAM cell, the read port of the proposed cell provides a virtual ground line running in parallel to the bit-lines. An internal driver of the sensing circuit releases the virtual ground line during the evaluation period to prevent the charge dissipation resulting in a raised voltage level. The reduced pre-charge level and the increased virtual ground lead to a reduced bit-line voltage swing and thus a bit-line power reduction. Access time, energy dissipation, and noise margin of the proposed sensing circuit are compared with conventional sensing circuits from the literature for different numbers of memory cells connected to the bit-line. It is shown, that for a specific number of memory cells per bit-line the proposed circuit achieves fastest access time at low power operation.

scholarly journals Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 33
Author(s):  
Bharathi Raj Muthu ◽  
Ewins Pon Pushpa ◽  
Vaithiyanathan Dhandapani ◽  
Kamala Jayaraman ◽  
Hemalatha Vasanthakumar ◽  
...  
Keyword(s):  
Soft Errors ◽  
Memory Cell ◽  
Soft Error ◽  
Access Time ◽  
Electronic Systems ◽  
Memory Cells ◽  
Noise Margin ◽  
Sram Cell ◽  
Driver Circuit ◽  
Radiation Hardened

Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray’s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET’s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals A Technique for Designing Variation Resilient Subthreshold Sram Cell

2013 ◽  
Vol 14 (1) ◽  
Author(s):  
Aminul Islam
Keyword(s):  
Process Variations ◽  
Access Time ◽  
Static Noise Margin ◽  
Design Metrics ◽  
Random Dopant Fluctuation ◽  
Noise Margin ◽  
Sram Cell ◽  
Transmission Gates ◽  
The Cost ◽  
Static Noise

This paper presents a technique for designing a variability aware subthreshold SRAM cell. The architecture of the proposed cell is similar to the standard read-decoupled 8-transistor (RD8T) SRAM cell with the exception that the access FETS are replaced with transmission gates (TGs). In this work, various design metrics are assessed and compared with RD8T SRAM cell. The proposed design offers 2.14× and 1.75× improvement in TRA (read access time) and TWA (write access time) respectively compared with RD8T. It proves its robustness against process variations by featuring narrower spread in TRA distribution (2.35×) and TWA distribution (3.79×) compared with RD8T. The proposed bitcell offers 1.16× higher read current (IREAD) and 1.64× lower bitline leakage current (ILEAK) respectively compared with RD8T. It also shows its robustness by offering 1.34× (1.58×) tighter spread in IREAD (ILEAK) compared with RD8T. It exhibits 1.42× larger IREAD to ILEAK ratio. It shows 2.2× higher frequency @ 250 mV with read bitline capacitance of 10 fF. Besides, the proposed bitcell achieves same read stability and write-ability as that of RD8T at the cost of 3 extra transistors. The leakage power of the proposed design is close to that of RD8T.   ABSTRAK: Kertas kerja ini membentangkan teknik merekabentuk sel bawah ambang SRAM yang bolehubah. Senibina sel yang dicadangkan adalah sama dengan sel SRAM 8-transistor (RD8T) “pisahan-bacaan” piawai kecuali FET akses  digantikan dengan sel pintu transmisi (TGs). Di dalam kajian ini, beberapa metrik rekabentuk dinilai dan dibandingkan dengan sel RD8T SRAM. Rekabentuk yang dicadangkan menawarkan  peningkatan 2.14× dan 1.75×  dalam TRA (masa akses baca) dan TWA (masa akses tulis) berbanding dengan RD8T. Ia membuktikan kekukuhan variasi proses dengan menampilkan tebaran yang lebih sempit dalam pengagihan TRA (2.35 ×) dan pengagihan TWA (3.79 ×) berbanding dengan RD8T. Sel-Bit yang dicadangkan mempunyai arus baca 1.16 × lebih tinggi  (IREAD) dan arus bocor bitline 1.64 × lebih rendah (ILEAK) berbanding dengan RD8T. Ia juga membuktikan kekukuhan dengan menawarkan 1.34 × (1.58 ×) penyebaran sempit di IREAD (ILEAK) berbanding dengan RD8T dan nisbah IREAD / ILEAK 1.42 × lebih besar. Ia menunjukkan kekerapan 2.2 × lebih tinggi pada 250 mV dengan kemuatan membaca bitline sebanyak 10 fF. Selain itu, sel bit yang dicadangkan mencapai kestabilan membaca dan keupayaan menulis yang sama seperti RD8T dengan kos tambahan 3 transistor. Kebocoran kuasa  rekabentuk yang dicadangkan hampir sama dengan RD8T. KEYWORDS: variability; robust, subthreshold; random dopant fluctuation (RDF); read static noise margin (RSNM); write static noise margin (WSNM).

scholarly journals VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY

2011 ◽  
Vol 12 (1) ◽  
pp. 13-30 ◽  
Author(s):  
Aminul Islam ◽  
Mohd. Hasan
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Static Random Access Memory ◽  
Access Time ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Pvt Variations ◽  
Static Noise

This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM).

Variability aware FinFET SRAM cell with improved stability and power for low power applications

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 196-207
Author(s):  
Shilpi Birla
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Leakage Power ◽  
Static Noise Margin ◽  
Content Type ◽  
Noise Margin ◽  
Sram Cell ◽  
Memory Circuits ◽  
The Stability ◽  
Static Noise

Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits. Design/methodology/approach In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. Findings The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384  mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed. Research limitations/implications The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used. Practical implications SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array. Social implications The cell can be used for SRAM memory for low power consumptions. Originality/value The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

A Novel Darlington-Based 8T CNTFET SRAM Cell for Low Power Applications

2021 ◽  
pp. 2150213
Author(s):  
M. Elangovan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Simulation Tool ◽  
Stanford University ◽  
Memory Cells ◽  
Power Performance ◽  
Dynamic Power ◽  
Memory Design ◽  
Noise Margin ◽  
Sram Cell

The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm

2013 ◽  
Vol 22 (08) ◽  
pp. 1350069 ◽  
Author(s):  
ABHIJIT SIL ◽  
KRISHNA PRASAD BALUSU ◽  
CHANDRA SEKHAR GURRAM ◽  
MAGDY BAYOUMI
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Supply Voltage ◽  
Access Time ◽  
Pipeline Architecture ◽  
Noise Margin ◽  
Sram Cell ◽  
Sram Design ◽  
Cell Current ◽  
Stability Issues

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100 nm technology. In this paper, we present a highly stable 2-port 8T SRAM cell for high speed application in 65 nm technology. The proposed design provides high stability under simultaneous read/write disturbed access without reducing the I cell . The cell characteristic is extensively examined under random variation. The dynamic read noise margin is improved by 95% over conventional dual port SRAM. The zero-precharge sensing and virtual ground scheme reduce read path leakage current by 95% over conventional high precharge 2-port SRAM cell. The cell current is improved by 52% over conventional design. Finally, an 8 Kb bit-interleaved 2-stage pipelined SRAM architecture is presented using proposed cell. The 2-stage pipeline architecture provides data transfer bandwidth of 3.1 GB/s. Area-efficient 2-stage decoder layout helps to avoid pseudo read problem in unselected cells without sacrificing memory access time.

scholarly journals A New 8T SRAM Circuit with Low Leakage and High Data Stability Idle Mode at 70nm Technology

2017 ◽  
Vol 10 (1) ◽  
pp. 86-93 ◽  
Author(s):  
P Raikwal ◽  
V Neema ◽  
A Verma
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
High Threshold ◽  
Idle Mode ◽  
High Data ◽  
Low Leakage ◽  
Noise Margin ◽  
Threshold Voltages ◽  
Sram Cell ◽  
Low Threshold

Memory has been facing several problems in which the leakage current is the most severe. Many techniques have been proposed to withstand leakage control such as power gating and ground gating. In this paper a new 8T SRAM cell, which adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high hold static noise margin. The proposed cell with low threshold voltage, high threshold voltage and dual threshold voltage are used to effectively reduce leakage current, and delay. Additionally, the comparison has been performed between conventional 6T SRAM cell and the new 8T SRAM cell. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit which is very less as compare to conventional 6T SRAM cell with sleep and hold transistors and with different β ratio. The proposed new 8T SRAM cell shows highest noise immunity 0.329mv during hold state. Furthermore, the proposed new 8T SRAM circuit represents minimum read and write access delays 114.13ps and 38.56ps respectively as compare to conventional 6T SRAM cell with different threshold voltages and β ratio.

Effect of Threshold Roll-Off on Static Noise Margin of Sram Cell

2018 ◽  
Author(s):  
Sunil Kumar Ojha ◽  
O.P. Singh ◽  
G.R. Mishra ◽  
P.R. Vaya
Keyword(s):  
Circuit Design ◽  
Threshold Voltage ◽  
Channel Length ◽  
Small Scale ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Channel Reduction ◽  
On Chip ◽  
Static Noise

Thethreshold roll-off is a vital phenomena to be considered for any low-power and small-scale circuit design. With the advancement of the fabrication processes the channel length of the transistors is reducing rapidly, this reduction in the channel length affects the threshold voltage of the transistors very severely. To evaluate the effect of channel reduction on the threshold voltage this paper analyzes the threshold roll-off by taking SRAM cell into consideration. The reason behind choosing SRAM cell is that now the IC’s are fabricated using system on chip (SOC) design technique and currently approximately 70-80% of the SOC area are covered by memories only. One of the most important Figure of Merit for SRAM cell is its Static Noise Margin (SNM) and hence the effect of threshold-roll is implemented with respect to SNM of the SRAM cell.

scholarly journals Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Priya Gupta ◽  
Anu Gupta ◽  
Abhijit Asati
Keyword(s):  
Supply Voltage ◽  
Access Time ◽  
Power Supply Voltage ◽  
Subthreshold Region ◽  
Technology Node ◽  
Noise Margin ◽  
Sram Cell ◽  
Margin Distribution ◽  
Cell Stability ◽  
Pass Transistor

The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in hold mode. The proposed 8T SRAM cell shows improvements in terms of 7.735x narrower spread in average standby power, 2.61x less in averageTWA(write access time), and 1.07x less in averageTRA(read access time) at supply voltage varying from 0.3 V to 0.5 V as compared to 6T SRAM equivalent at 45 nm technology node. Thus, comparative analysis shows that the proposed design has a significant improvement, thereby achieving high cell stability at 45 nm technology node.

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