Ever since their birth in the late 60s, the integrated circuits based on complementary CMOS technology have dominated the VLSI scene, primarily due to their main distinctive feature which is the low power dissipation. In recent years, however, the ongoing increase in the number of processing elements (in perfect agreement with Moore’s law) and operating frequency, coupled with the decrease in feature size and supply voltage, have augmented the amounts of dissipated power and accentuated the associated reliability problems. Addressing these issues is compulsory and presents one of the biggest challenges facing the integrated circuit industry in the foreseeable future. This has brought forward the need for tools and methods that perform efficient analysis and estimation of the overall power requirements of a particular integrated circuit during the design phase. In contrast, however, to the other two basic design parameters, namely the delay and occupation area, the quantity of power is extremely difficult to estimate as it depends on the specific input vectors that inflict a transition in the circuit’s logic state. Since, as is well known, the total number of input vectors bears an exponential relationship with the number of primary inputs and is therefore prohibitively large to conduct an exhaustive examination, the only viable solution is to employ statistical techniques which transfer the burden from a large population to a much smaller sample. The component of power in CMOS circuits manifests in two different forms, that is the average and maximum power, both of which demand separate approaches for their estimation and have their own special significance within the broader design framework. In particular, the average power is the form that primarily defines the rating of power dissipation in a specified circuit, whereas the maximum power is related with arguably the biggest existing reliability problem which is the voltage drop on the power supply wires. The estimation of average power from a statistical viewpoint can be reduced to the classic problem of estimation of a statistical average (i.e. the average of a statistical population) on the basis of the central limit theorem (CLT), and as such, it is largely considered as a resolved matter in the literature. On the other hand, however, the estimation of maximum power still remains an open issue as the corresponding problem of estimation of a population maximum falls into a relatively unexploited area of statistics that is known as (asymptotic) extreme value theory. This particular theory is considerably more complex and not as readily applicable as the theory behind the CLT, but what is more important, it involves certain subtle points which if not addressed properly could seriously affect the overall estimation results. The present thesis attempts to fill this gap with a primary target that is twofold. At first, the development of a sound and efficient method for the estimation of a general population maximum using the aforementioned extreme value theory is pursued, while secondly this universal method is applied on the estimation of maximum power in CMOS VLSI circuits. The method being developed is mathematically rigorous and based on a solid theoretical foundation, while in order to successfully deal with the intricate points of the theory incorporates some unique concepts and techniques which appear for the first time in the literature. The whole development is carried out in full comparison with the established approach for estimation of a statistical average and its respective application to average power estimation. Apart from providing an effective solution to the problem of maximum power estimation, the proposed method boasts some very attractive properties such as relatively small number of required input vectors that does not depend on the circuit size or complexity, “a priori” specifiable error and confidence levels for the final estimate, remarkably simple algorithmic implementation that does not include time- consuming iterative loops, and lastly simulation-based operation which ensures the necessary accuracy in the assembly of power data as well as easy incorporation within any design flow for digital integrated circuits. All the above are being supported by experimental results upon a set of standard benchmark circuits. Moreover, the necessary guidelines for the exploitation of the method to the addressing of the voltage drop problem are given, thus laying the foundation for future work in the area.
4-bit Carry Look Ahead Adder Using MGDI Technique
