Voltage scaling – a novel approach for crosstalk reduction in global VLSI interconnects

2007 ◽  
Vol 24 (1) ◽  
pp. 40-45 ◽  
Author(s):  
B.K. Kaushik ◽  
S. Sarkar ◽  
R.P. Agarwal ◽  
R.C. Joshi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Reducing Power ◽  
Propagation Delay ◽  
Voltage Scaling ◽  
Content Type ◽  
New Era ◽  
Novel Approach ◽  
Crosstalk Reduction ◽  
Power Delay Product

PurposeTo analyze the effect of voltage scaling on crosstalk.Design/methodology/approachVoltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. VA (input at aggressor node A) and VB (input at victim node B) switching in same direction; VA is switching and VB at static low; VA and VB are switching in opposite direction; VA is switching and VB at static high.FindingsIt is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.Originality/valueVoltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.

scholarly journals Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1718
Author(s):  
Neha Gupta ◽  
Ambika Prasad Shah ◽  
Sajid Khan ◽  
Santosh Kumar Vishvakarma ◽  
Michael Waltl ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Functional Improvement ◽  
Scaling Technique ◽  
Iot Applications ◽  
Sram Cell ◽  
Improved Stability ◽  
Supply Voltage Scaling ◽  
Power Delay Product

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

Design of ternary subtractor using multiplexers

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tulasi Naga Jyothi Kolanti ◽  
Vasundhara Patel K.S.
Keyword(s):  
Field Effect Transistors ◽  
Process Variations ◽  
Propagation Delay ◽  
Channel Length ◽  
Binary Decision ◽  
Content Type ◽  
The Stability ◽  
Power Delay Product ◽  
Ternary Decision Diagram ◽  
Logic Functions

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

Role of Through Silicon Via in 3D Integration: Impact on Delay and Power

2020 ◽  
pp. 2150051
Author(s):  
Shivangi Chandrakar ◽  
Deepika Gupta ◽  
Manoj Kumar Majumder
Keyword(s):  
Power Dissipation ◽  
Three Dimensional ◽  
Propagation Delay ◽  
Model Parameters ◽  
3D Integration ◽  
Coupling Behavior ◽  
Power Delay Product ◽  
Silicon Vias ◽  
The Impact

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sandeep Garg ◽  
Tarun Kumar Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Maximum Delay ◽  
Average Power Consumption

Purpose This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis. Design/methodology/approach In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE. Findings The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques. Originality/value The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

scholarly journals A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Nabihah Ahmad ◽  
Rezaul Hasan
Keyword(s):  
Circuit Design ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Cmos Process ◽  
Xor Gate ◽  
Power Efficient ◽  
Pass Transistor ◽  
Full Swing

A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.

POWER REDUCTION TECHNIQUE USING MULTIPLE SUPPLY VOLTAGE AND SWITCHING ACTIVITY ANALYSIS

2013 ◽  
Vol 22 (02) ◽  
pp. 1250079
Author(s):  
BASHAR HADDAD ◽  
AMIN JARRAH
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Critical Path ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Activity Analysis ◽  
Vlsi Circuits ◽  
Total Power ◽  
Switching Activity ◽  
Activity Factor

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V CC ) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V CCs to different elements.

scholarly journals Performance evaluation of high speed compressors for high speed multipliers

2011 ◽  
Vol 8 (3) ◽  
pp. 293-306 ◽  
Author(s):  
Ravi Nirlakalla ◽  
Rao Subba ◽  
Talari Jayachandra-Prasad
Keyword(s):  
Performance Evaluation ◽  
High Speed ◽  
Supply Voltage ◽  
Critical Path ◽  
Digital Signal ◽  
Propagation Delay ◽  
Booth Multiplier ◽  
Half Adder ◽  
Power Delay Product ◽  
Wallace Tree Multiplier

This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25?C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only.

Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects

2015 ◽  
Vol 13 (3) ◽  
pp. 486-498 ◽  
Author(s):  
S.K. Verma ◽  
B.K. Kaushik
Keyword(s):  
Power Dissipation ◽  
Propagation Delay ◽  
Worst Case ◽  
Content Type ◽  
Vlsi Interconnects ◽  
Overall Performance ◽  
Encoding Method ◽  
Simultaneous Switching

Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects. Findings – It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely. Research limitations/implications – In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions. Practical implications – The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation. Originality/value – This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes.

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