Multi-Site Full Thickness Backside Focused Ion Beam (FIB) Editing for eDRAM Array Address Descramble Verification

Focused Ion Beam (FIB) modification for chip repair, layout verification, and internal signal probing has become an integral part of the process for bringing advanced products to market. As devices become more complex, with more levels of dense, thick upper power planes and tighter lower point-to-point wiring and device geometries, primary FIB access through the backside of the chip has become the only viable approach. And the pervasive switch to flip-chip solder bump mounting of chips to modules and chip to chip stacked die has made the backside editing approach ever more sensible by placing the unobstructed backside of the die within easy reach. Sample preparation for backside edit, however, has become a growing problem. Mechanical thinning of the silicon to speed trenching time can be problematic on highly stressed chips as there is a high risk of silicon cracking. Plus there are situations in which die strength must be preserved to enable the transfer of an edited die to a new substrate. While single point full thickness silicon editing has been demonstrated, the need to make multiple trenches for repetitive edits can be extremely time consuming when using conventional FIB bulk removal recipes. A single logic error often gets repeated in each core of a multi-core chip, and may need to be fixed at each location. Verification of existing SRAM and the introduction of embedded DRAM (eDRAM) for large blocks of L3 cache on high end microprocessors meant that the FIB lab would be called upon to provide layout checking services on a number of designs. Clearly, a better method for rapid mass silicon removal needed to be developed to keep multi-point backside editing viable. Through an extensive set of experiments we were able to develop a process that can sustain a removal rate of 10 million cubic microns of silicon per minute, enabling full thickness trenches in as little as 25 minutes. As will be shown, this preparation technique was successfully used to ensure the bit map descramble accuracy of multiple eDRAM array blocks in several cores, and to help evaluate test coverage.